138 строки
4.7 KiB
C
138 строки
4.7 KiB
C
/*
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* include/asm-v850/anna.h -- Anna V850E2 evaluation cpu chip/board
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_ANNA_H__
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#define __V850_ANNA_H__
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#include <asm/v850e2.h> /* Based on V850E2 core. */
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#define CPU_MODEL "v850e2/anna"
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#define CPU_MODEL_LONG "NEC V850E2/Anna"
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#define PLATFORM "anna"
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#define PLATFORM_LONG "NEC/Midas lab V850E2/Anna evaluation board"
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#define CPU_CLOCK_FREQ 200000000 /* 200MHz */
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#define SYS_CLOCK_FREQ 33300000 /* 33.3MHz */
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/* 1MB of static RAM. This memory is mirrored 64 times. */
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#define SRAM_ADDR 0x04000000
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#define SRAM_SIZE 0x00100000 /* 1MB */
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/* 64MB of DRAM. */
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#define SDRAM_ADDR 0x08000000
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#define SDRAM_SIZE 0x04000000 /* 64MB */
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/* For <asm/page.h> */
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#define PAGE_OFFSET SRAM_ADDR
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/* We use on-chip RAM, for a few miscellaneous variables that must be
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accessible using a load instruction relative to R0. The Anna chip has
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128K of `dLB' ram nominally located at 0xFFF00000, but it's mirrored
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every 128K, so we can use the `last mirror' (except for the portion at
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the top which is overridden by I/O space). In addition, the early
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sample chip we're using has lots of memory errors in the dLB ram, so we
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use a specially chosen location that has at least 20 bytes of contiguous
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valid memory (xxxF0020 - xxxF003F). */
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#define R0_RAM_ADDR 0xFFFF8020
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/* Anna specific control registers. */
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#define ANNA_ILBEN_ADDR 0xFFFFF7F2
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#define ANNA_ILBEN (*(volatile u16 *)ANNA_ILBEN_ADDR)
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/* I/O port P0-P3. */
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/* Direct I/O. Bits 0-7 are pins Pn0-Pn7. */
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#define ANNA_PORT_IO_ADDR(n) (0xFFFFF400 + (n) * 2)
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#define ANNA_PORT_IO(n) (*(volatile u8 *)ANNA_PORT_IO_ADDR(n))
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/* Port mode (for direct I/O, 0 = output, 1 = input). */
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#define ANNA_PORT_PM_ADDR(n) (0xFFFFF410 + (n) * 2)
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#define ANNA_PORT_PM(n) (*(volatile u8 *)ANNA_PORT_PM_ADDR(n))
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/* Hardware-specific interrupt numbers (in the kernel IRQ namespace). */
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#define IRQ_INTP(n) (n) /* Pnnn (pin) interrupts 0-15 */
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#define IRQ_INTP_NUM 16
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#define IRQ_INTOV(n) (0x10 + (n)) /* 0-2 */
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#define IRQ_INTOV_NUM 2
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#define IRQ_INTCCC(n) (0x12 + (n))
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#define IRQ_INTCCC_NUM 4
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#define IRQ_INTCMD(n) (0x16 + (n)) /* interval timer interrupts 0-5 */
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#define IRQ_INTCMD_NUM 6
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#define IRQ_INTDMA(n) (0x1C + (n)) /* DMA interrupts 0-3 */
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#define IRQ_INTDMA_NUM 4
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#define IRQ_INTDMXER 0x20
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#define IRQ_INTSRE(n) (0x21 + (n)*3) /* UART 0-1 reception error */
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#define IRQ_INTSRE_NUM 2
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#define IRQ_INTSR(n) (0x22 + (n)*3) /* UART 0-1 reception completion */
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#define IRQ_INTSR_NUM 2
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#define IRQ_INTST(n) (0x23 + (n)*3) /* UART 0-1 transmission completion */
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#define IRQ_INTST_NUM 2
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#define NUM_CPU_IRQS 64
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#ifndef __ASSEMBLY__
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/* Initialize chip interrupts. */
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extern void anna_init_irqs (void);
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#endif
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/* Anna UART details (basically the same as the V850E/MA1, but 2 channels). */
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#define V850E_UART_NUM_CHANNELS 2
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#define V850E_UART_BASE_FREQ (SYS_CLOCK_FREQ / 2)
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#define V850E_UART_CHIP_NAME "V850E2/NA85E2A"
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/* This is the UART channel that's actually connected on the board. */
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#define V850E_UART_CONSOLE_CHANNEL 1
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/* This is a function that gets called before configuring the UART. */
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#define V850E_UART_PRE_CONFIGURE anna_uart_pre_configure
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#ifndef __ASSEMBLY__
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extern void anna_uart_pre_configure (unsigned chan,
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unsigned cflags, unsigned baud);
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#endif
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/* This board supports RTS/CTS for the on-chip UART, but only for channel 1. */
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/* CTS for UART channel 1 is pin P37 (bit 7 of port 3). */
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#define V850E_UART_CTS(chan) ((chan) == 1 ? !(ANNA_PORT_IO(3) & 0x80) : 1)
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/* RTS for UART channel 1 is pin P07 (bit 7 of port 0). */
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#define V850E_UART_SET_RTS(chan, val) \
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do { \
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if (chan == 1) { \
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unsigned old = ANNA_PORT_IO(0); \
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if (val) \
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ANNA_PORT_IO(0) = old & ~0x80; \
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else \
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ANNA_PORT_IO(0) = old | 0x80; \
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} \
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} while (0)
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/* Timer C details. */
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#define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
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/* Timer D details (the Anna actually has 5 of these; should change later). */
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#define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
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#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
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#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
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#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
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#define V850E_TIMER_D_BASE_FREQ SYS_CLOCK_FREQ
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#define V850E_TIMER_D_TMCD_CS_MIN 1 /* min 2^1 divider */
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#endif /* __V850_ANNA_H__ */
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