512 строки
23 KiB
Plaintext
512 строки
23 KiB
Plaintext
The MSI Driver Guide HOWTO
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Tom L Nguyen tom.l.nguyen@intel.com
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10/03/2003
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Revised Feb 12, 2004 by Martine Silbermann
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email: Martine.Silbermann@hp.com
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Revised Jun 25, 2004 by Tom L Nguyen
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1. About this guide
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This guide describes the basics of Message Signaled Interrupts (MSI),
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the advantages of using MSI over traditional interrupt mechanisms,
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and how to enable your driver to use MSI or MSI-X. Also included is
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a Frequently Asked Questions (FAQ) section.
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1.1 Terminology
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PCI devices can be single-function or multi-function. In either case,
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when this text talks about enabling or disabling MSI on a "device
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function," it is referring to one specific PCI device and function and
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not to all functions on a PCI device (unless the PCI device has only
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one function).
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2. Copyright 2003 Intel Corporation
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3. What is MSI/MSI-X?
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Message Signaled Interrupt (MSI), as described in the PCI Local Bus
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Specification Revision 2.3 or later, is an optional feature, and a
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required feature for PCI Express devices. MSI enables a device function
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to request service by sending an Inbound Memory Write on its PCI bus to
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the FSB as a Message Signal Interrupt transaction. Because MSI is
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generated in the form of a Memory Write, all transaction conditions,
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such as a Retry, Master-Abort, Target-Abort or normal completion, are
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supported.
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A PCI device that supports MSI must also support pin IRQ assertion
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interrupt mechanism to provide backward compatibility for systems that
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do not support MSI. In systems which support MSI, the bus driver is
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responsible for initializing the message address and message data of
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the device function's MSI/MSI-X capability structure during device
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initial configuration.
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An MSI capable device function indicates MSI support by implementing
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the MSI/MSI-X capability structure in its PCI capability list. The
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device function may implement both the MSI capability structure and
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the MSI-X capability structure; however, the bus driver should not
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enable both.
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The MSI capability structure contains Message Control register,
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Message Address register and Message Data register. These registers
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provide the bus driver control over MSI. The Message Control register
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indicates the MSI capability supported by the device. The Message
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Address register specifies the target address and the Message Data
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register specifies the characteristics of the message. To request
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service, the device function writes the content of the Message Data
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register to the target address. The device and its software driver
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are prohibited from writing to these registers.
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The MSI-X capability structure is an optional extension to MSI. It
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uses an independent and separate capability structure. There are
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some key advantages to implementing the MSI-X capability structure
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over the MSI capability structure as described below.
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- Support a larger maximum number of vectors per function.
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- Provide the ability for system software to configure
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each vector with an independent message address and message
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data, specified by a table that resides in Memory Space.
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- MSI and MSI-X both support per-vector masking. Per-vector
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masking is an optional extension of MSI but a required
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feature for MSI-X. Per-vector masking provides the kernel the
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ability to mask/unmask a single MSI while running its
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interrupt service routine. If per-vector masking is
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not supported, then the device driver should provide the
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hardware/software synchronization to ensure that the device
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generates MSI when the driver wants it to do so.
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4. Why use MSI?
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As a benefit to the simplification of board design, MSI allows board
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designers to remove out-of-band interrupt routing. MSI is another
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step towards a legacy-free environment.
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Due to increasing pressure on chipset and processor packages to
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reduce pin count, the need for interrupt pins is expected to
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diminish over time. Devices, due to pin constraints, may implement
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messages to increase performance.
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PCI Express endpoints uses INTx emulation (in-band messages) instead
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of IRQ pin assertion. Using INTx emulation requires interrupt
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sharing among devices connected to the same node (PCI bridge) while
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MSI is unique (non-shared) and does not require BIOS configuration
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support. As a result, the PCI Express technology requires MSI
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support for better interrupt performance.
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Using MSI enables the device functions to support two or more
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vectors, which can be configured to target different CPUs to
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increase scalability.
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5. Configuring a driver to use MSI/MSI-X
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By default, the kernel will not enable MSI/MSI-X on all devices that
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support this capability. The CONFIG_PCI_MSI kernel option
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must be selected to enable MSI/MSI-X support.
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5.1 Including MSI/MSI-X support into the kernel
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To allow MSI/MSI-X capable device drivers to selectively enable
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MSI/MSI-X (using pci_enable_msi()/pci_enable_msix() as described
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below), the VECTOR based scheme needs to be enabled by setting
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CONFIG_PCI_MSI during kernel config.
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Since the target of the inbound message is the local APIC, providing
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CONFIG_X86_LOCAL_APIC must be enabled as well as CONFIG_PCI_MSI.
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5.2 Configuring for MSI support
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Due to the non-contiguous fashion in vector assignment of the
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existing Linux kernel, this version does not support multiple
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messages regardless of a device function is capable of supporting
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more than one vector. To enable MSI on a device function's MSI
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capability structure requires a device driver to call the function
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pci_enable_msi() explicitly.
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5.2.1 API pci_enable_msi
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int pci_enable_msi(struct pci_dev *dev)
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With this new API, a device driver that wants to have MSI
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enabled on its device function must call this API to enable MSI.
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A successful call will initialize the MSI capability structure
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with ONE vector, regardless of whether a device function is
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capable of supporting multiple messages. This vector replaces the
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pre-assigned dev->irq with a new MSI vector. To avoid a conflict
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of the new assigned vector with existing pre-assigned vector requires
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a device driver to call this API before calling request_irq().
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5.2.2 API pci_disable_msi
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void pci_disable_msi(struct pci_dev *dev)
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This API should always be used to undo the effect of pci_enable_msi()
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when a device driver is unloading. This API restores dev->irq with
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the pre-assigned IOAPIC vector and switches a device's interrupt
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mode to PCI pin-irq assertion/INTx emulation mode.
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Note that a device driver should always call free_irq() on the MSI vector
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that it has done request_irq() on before calling this API. Failure to do
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so results in a BUG_ON() and a device will be left with MSI enabled and
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leaks its vector.
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5.2.3 MSI mode vs. legacy mode diagram
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The below diagram shows the events which switch the interrupt
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mode on the MSI-capable device function between MSI mode and
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PIN-IRQ assertion mode.
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------------ pci_enable_msi ------------------------
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| MSI MODE | | PIN-IRQ ASSERTION MODE |
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------------ pci_disable_msi ------------------------
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Figure 1. MSI Mode vs. Legacy Mode
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In Figure 1, a device operates by default in legacy mode. Legacy
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in this context means PCI pin-irq assertion or PCI-Express INTx
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emulation. A successful MSI request (using pci_enable_msi()) switches
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a device's interrupt mode to MSI mode. A pre-assigned IOAPIC vector
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stored in dev->irq will be saved by the PCI subsystem and a new
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assigned MSI vector will replace dev->irq.
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To return back to its default mode, a device driver should always call
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pci_disable_msi() to undo the effect of pci_enable_msi(). Note that a
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device driver should always call free_irq() on the MSI vector it has
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done request_irq() on before calling pci_disable_msi(). Failure to do
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so results in a BUG_ON() and a device will be left with MSI enabled and
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leaks its vector. Otherwise, the PCI subsystem restores a device's
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dev->irq with a pre-assigned IOAPIC vector and marks the released
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MSI vector as unused.
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Once being marked as unused, there is no guarantee that the PCI
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subsystem will reserve this MSI vector for a device. Depending on
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the availability of current PCI vector resources and the number of
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MSI/MSI-X requests from other drivers, this MSI may be re-assigned.
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For the case where the PCI subsystem re-assigns this MSI vector to
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another driver, a request to switch back to MSI mode may result
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in being assigned a different MSI vector or a failure if no more
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vectors are available.
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5.3 Configuring for MSI-X support
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Due to the ability of the system software to configure each vector of
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the MSI-X capability structure with an independent message address
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and message data, the non-contiguous fashion in vector assignment of
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the existing Linux kernel has no impact on supporting multiple
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messages on an MSI-X capable device functions. To enable MSI-X on
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a device function's MSI-X capability structure requires its device
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driver to call the function pci_enable_msix() explicitly.
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The function pci_enable_msix(), once invoked, enables either
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all or nothing, depending on the current availability of PCI vector
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resources. If the PCI vector resources are available for the number
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of vectors requested by a device driver, this function will configure
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the MSI-X table of the MSI-X capability structure of a device with
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requested messages. To emphasize this reason, for example, a device
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may be capable for supporting the maximum of 32 vectors while its
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software driver usually may request 4 vectors. It is recommended
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that the device driver should call this function once during the
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initialization phase of the device driver.
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Unlike the function pci_enable_msi(), the function pci_enable_msix()
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does not replace the pre-assigned IOAPIC dev->irq with a new MSI
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vector because the PCI subsystem writes the 1:1 vector-to-entry mapping
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into the field vector of each element contained in a second argument.
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Note that the pre-assigned IOAPIC dev->irq is valid only if the device
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operates in PIN-IRQ assertion mode. In MSI-X mode, any attempt at
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using dev->irq by the device driver to request for interrupt service
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may result unpredictabe behavior.
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For each MSI-X vector granted, a device driver is responsible for calling
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other functions like request_irq(), enable_irq(), etc. to enable
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this vector with its corresponding interrupt service handler. It is
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a device driver's choice to assign all vectors with the same
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interrupt service handler or each vector with a unique interrupt
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service handler.
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5.3.1 Handling MMIO address space of MSI-X Table
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The PCI 3.0 specification has implementation notes that MMIO address
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space for a device's MSI-X structure should be isolated so that the
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software system can set different pages for controlling accesses to the
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MSI-X structure. The implementation of MSI support requires the PCI
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subsystem, not a device driver, to maintain full control of the MSI-X
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table/MSI-X PBA (Pending Bit Array) and MMIO address space of the MSI-X
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table/MSI-X PBA. A device driver is prohibited from requesting the MMIO
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address space of the MSI-X table/MSI-X PBA. Otherwise, the PCI subsystem
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will fail enabling MSI-X on its hardware device when it calls the function
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pci_enable_msix().
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5.3.2 Handling MSI-X allocation
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Determining the number of MSI-X vectors allocated to a function is
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dependent on the number of MSI capable devices and MSI-X capable
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devices populated in the system. The policy of allocating MSI-X
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vectors to a function is defined as the following:
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#of MSI-X vectors allocated to a function = (x - y)/z where
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x = The number of available PCI vector resources by the time
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the device driver calls pci_enable_msix(). The PCI vector
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resources is the sum of the number of unassigned vectors
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(new) and the number of released vectors when any MSI/MSI-X
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device driver switches its hardware device back to a legacy
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mode or is hot-removed. The number of unassigned vectors
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may exclude some vectors reserved, as defined in parameter
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NR_HP_RESERVED_VECTORS, for the case where the system is
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capable of supporting hot-add/hot-remove operations. Users
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may change the value defined in NR_HR_RESERVED_VECTORS to
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meet their specific needs.
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y = The number of MSI capable devices populated in the system.
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This policy ensures that each MSI capable device has its
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vector reserved to avoid the case where some MSI-X capable
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drivers may attempt to claim all available vector resources.
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z = The number of MSI-X capable devices populated in the system.
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This policy ensures that maximum (x - y) is distributed
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evenly among MSI-X capable devices.
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Note that the PCI subsystem scans y and z during a bus enumeration.
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When the PCI subsystem completes configuring MSI/MSI-X capability
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structure of a device as requested by its device driver, y/z is
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decremented accordingly.
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5.3.3 Handling MSI-X shortages
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For the case where fewer MSI-X vectors are allocated to a function
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than requested, the function pci_enable_msix() will return the
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maximum number of MSI-X vectors available to the caller. A device
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driver may re-send its request with fewer or equal vectors indicated
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in the return. For example, if a device driver requests 5 vectors, but
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the number of available vectors is 3 vectors, a value of 3 will be
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returned as a result of pci_enable_msix() call. A function could be
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designed for its driver to use only 3 MSI-X table entries as
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different combinations as ABC--, A-B-C, A--CB, etc. Note that this
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patch does not support multiple entries with the same vector. Such
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attempt by a device driver to use 5 MSI-X table entries with 3 vectors
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as ABBCC, AABCC, BCCBA, etc will result as a failure by the function
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pci_enable_msix(). Below are the reasons why supporting multiple
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entries with the same vector is an undesirable solution.
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- The PCI subsystem cannot determine the entry that
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generated the message to mask/unmask MSI while handling
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software driver ISR. Attempting to walk through all MSI-X
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table entries (2048 max) to mask/unmask any match vector
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is an undesirable solution.
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- Walking through all MSI-X table entries (2048 max) to handle
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SMP affinity of any match vector is an undesirable solution.
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5.3.4 API pci_enable_msix
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int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
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This API enables a device driver to request the PCI subsystem
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to enable MSI-X messages on its hardware device. Depending on
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the availability of PCI vectors resources, the PCI subsystem enables
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either all or none of the requested vectors.
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Argument 'dev' points to the device (pci_dev) structure.
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Argument 'entries' is a pointer to an array of msix_entry structs.
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The number of entries is indicated in argument 'nvec'.
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struct msix_entry is defined in /driver/pci/msi.h:
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struct msix_entry {
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u16 vector; /* kernel uses to write alloc vector */
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u16 entry; /* driver uses to specify entry */
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};
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A device driver is responsible for initializing the field 'entry' of
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each element with a unique entry supported by MSI-X table. Otherwise,
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-EINVAL will be returned as a result. A successful return of zero
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indicates the PCI subsystem completed initializing each of the requested
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entries of the MSI-X table with message address and message data.
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Last but not least, the PCI subsystem will write the 1:1
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vector-to-entry mapping into the field 'vector' of each element. A
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device driver is responsible for keeping track of allocated MSI-X
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vectors in its internal data structure.
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A return of zero indicates that the number of MSI-X vectors was
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successfully allocated. A return of greater than zero indicates
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MSI-X vector shortage. Or a return of less than zero indicates
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a failure. This failure may be a result of duplicate entries
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specified in second argument, or a result of no available vector,
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or a result of failing to initialize MSI-X table entries.
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5.3.5 API pci_disable_msix
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void pci_disable_msix(struct pci_dev *dev)
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This API should always be used to undo the effect of pci_enable_msix()
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when a device driver is unloading. Note that a device driver should
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always call free_irq() on all MSI-X vectors it has done request_irq()
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on before calling this API. Failure to do so results in a BUG_ON() and
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a device will be left with MSI-X enabled and leaks its vectors.
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5.3.6 MSI-X mode vs. legacy mode diagram
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The below diagram shows the events which switch the interrupt
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mode on the MSI-X capable device function between MSI-X mode and
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PIN-IRQ assertion mode (legacy).
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------------ pci_enable_msix(,,n) ------------------------
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| MSI-X MODE | | PIN-IRQ ASSERTION MODE |
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------------ pci_disable_msix ------------------------
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Figure 2. MSI-X Mode vs. Legacy Mode
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In Figure 2, a device operates by default in legacy mode. A
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successful MSI-X request (using pci_enable_msix()) switches a
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device's interrupt mode to MSI-X mode. A pre-assigned IOAPIC vector
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stored in dev->irq will be saved by the PCI subsystem; however,
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unlike MSI mode, the PCI subsystem will not replace dev->irq with
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assigned MSI-X vector because the PCI subsystem already writes the 1:1
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vector-to-entry mapping into the field 'vector' of each element
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specified in second argument.
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To return back to its default mode, a device driver should always call
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pci_disable_msix() to undo the effect of pci_enable_msix(). Note that
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a device driver should always call free_irq() on all MSI-X vectors it
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has done request_irq() on before calling pci_disable_msix(). Failure
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to do so results in a BUG_ON() and a device will be left with MSI-X
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enabled and leaks its vectors. Otherwise, the PCI subsystem switches a
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device function's interrupt mode from MSI-X mode to legacy mode and
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marks all allocated MSI-X vectors as unused.
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Once being marked as unused, there is no guarantee that the PCI
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subsystem will reserve these MSI-X vectors for a device. Depending on
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the availability of current PCI vector resources and the number of
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MSI/MSI-X requests from other drivers, these MSI-X vectors may be
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re-assigned.
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For the case where the PCI subsystem re-assigned these MSI-X vectors
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to other drivers, a request to switch back to MSI-X mode may result
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being assigned with another set of MSI-X vectors or a failure if no
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more vectors are available.
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5.4 Handling function implementing both MSI and MSI-X capabilities
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For the case where a function implements both MSI and MSI-X
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capabilities, the PCI subsystem enables a device to run either in MSI
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mode or MSI-X mode but not both. A device driver determines whether it
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wants MSI or MSI-X enabled on its hardware device. Once a device
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driver requests for MSI, for example, it is prohibited from requesting
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MSI-X; in other words, a device driver is not permitted to ping-pong
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between MSI mod MSI-X mode during a run-time.
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5.5 Hardware requirements for MSI/MSI-X support
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MSI/MSI-X support requires support from both system hardware and
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individual hardware device functions.
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5.5.1 System hardware support
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Since the target of MSI address is the local APIC CPU, enabling
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MSI/MSI-X support in the Linux kernel is dependent on whether existing
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system hardware supports local APIC. Users should verify that their
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system supports local APIC operation by testing that it runs when
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CONFIG_X86_LOCAL_APIC=y.
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In SMP environment, CONFIG_X86_LOCAL_APIC is automatically set;
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however, in UP environment, users must manually set
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CONFIG_X86_LOCAL_APIC. Once CONFIG_X86_LOCAL_APIC=y, setting
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CONFIG_PCI_MSI enables the VECTOR based scheme and the option for
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MSI-capable device drivers to selectively enable MSI/MSI-X.
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Note that CONFIG_X86_IO_APIC setting is irrelevant because MSI/MSI-X
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vector is allocated new during runtime and MSI/MSI-X support does not
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depend on BIOS support. This key independency enables MSI/MSI-X
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support on future IOxAPIC free platforms.
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5.5.2 Device hardware support
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The hardware device function supports MSI by indicating the
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MSI/MSI-X capability structure on its PCI capability list. By
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default, this capability structure will not be initialized by
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the kernel to enable MSI during the system boot. In other words,
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the device function is running on its default pin assertion mode.
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Note that in many cases the hardware supporting MSI have bugs,
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which may result in system hangs. The software driver of specific
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MSI-capable hardware is responsible for deciding whether to call
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pci_enable_msi or not. A return of zero indicates the kernel
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successfully initialized the MSI/MSI-X capability structure of the
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device function. The device function is now running on MSI/MSI-X mode.
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5.6 How to tell whether MSI/MSI-X is enabled on device function
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At the driver level, a return of zero from the function call of
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pci_enable_msi()/pci_enable_msix() indicates to a device driver that
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|
its device function is initialized successfully and ready to run in
|
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MSI/MSI-X mode.
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|
|
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At the user level, users can use the command 'cat /proc/interrupts'
|
|
to display the vectors allocated for devices and their interrupt
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|
MSI/MSI-X modes ("PCI-MSI"/"PCI-MSI-X"). Below shows MSI mode is
|
|
enabled on a SCSI Adaptec 39320D Ultra320 controller.
|
|
|
|
CPU0 CPU1
|
|
0: 324639 0 IO-APIC-edge timer
|
|
1: 1186 0 IO-APIC-edge i8042
|
|
2: 0 0 XT-PIC cascade
|
|
12: 2797 0 IO-APIC-edge i8042
|
|
14: 6543 0 IO-APIC-edge ide0
|
|
15: 1 0 IO-APIC-edge ide1
|
|
169: 0 0 IO-APIC-level uhci-hcd
|
|
185: 0 0 IO-APIC-level uhci-hcd
|
|
193: 138 10 PCI-MSI aic79xx
|
|
201: 30 0 PCI-MSI aic79xx
|
|
225: 30 0 IO-APIC-level aic7xxx
|
|
233: 30 0 IO-APIC-level aic7xxx
|
|
NMI: 0 0
|
|
LOC: 324553 325068
|
|
ERR: 0
|
|
MIS: 0
|
|
|
|
6. FAQ
|
|
|
|
Q1. Are there any limitations on using the MSI?
|
|
|
|
A1. If the PCI device supports MSI and conforms to the
|
|
specification and the platform supports the APIC local bus,
|
|
then using MSI should work.
|
|
|
|
Q2. Will it work on all the Pentium processors (P3, P4, Xeon,
|
|
AMD processors)? In P3 IPI's are transmitted on the APIC local
|
|
bus and in P4 and Xeon they are transmitted on the system
|
|
bus. Are there any implications with this?
|
|
|
|
A2. MSI support enables a PCI device sending an inbound
|
|
memory write (0xfeexxxxx as target address) on its PCI bus
|
|
directly to the FSB. Since the message address has a
|
|
redirection hint bit cleared, it should work.
|
|
|
|
Q3. The target address 0xfeexxxxx will be translated by the
|
|
Host Bridge into an interrupt message. Are there any
|
|
limitations on the chipsets such as Intel 8xx, Intel e7xxx,
|
|
or VIA?
|
|
|
|
A3. If these chipsets support an inbound memory write with
|
|
target address set as 0xfeexxxxx, as conformed to PCI
|
|
specification 2.3 or latest, then it should work.
|
|
|
|
Q4. From the driver point of view, if the MSI is lost because
|
|
of errors occurring during inbound memory write, then it may
|
|
wait forever. Is there a mechanism for it to recover?
|
|
|
|
A4. Since the target of the transaction is an inbound memory
|
|
write, all transaction termination conditions (Retry,
|
|
Master-Abort, Target-Abort, or normal completion) are
|
|
supported. A device sending an MSI must abide by all the PCI
|
|
rules and conditions regarding that inbound memory write. So,
|
|
if a retry is signaled it must retry, etc... We believe that
|
|
the recommendation for Abort is also a retry (refer to PCI
|
|
specification 2.3 or latest).
|