510 строки
17 KiB
C
510 строки
17 KiB
C
/*
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* Copyright (c) 2015, Sony Mobile Communications AB.
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* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/of_regulator.h>
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#include <linux/soc/qcom/smd-rpm.h>
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struct qcom_rpm_reg {
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struct device *dev;
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struct qcom_smd_rpm *rpm;
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u32 type;
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u32 id;
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struct regulator_desc desc;
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int is_enabled;
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int uV;
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};
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struct rpm_regulator_req {
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__le32 key;
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__le32 nbytes;
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__le32 value;
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};
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#define RPM_KEY_SWEN 0x6e657773 /* "swen" */
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#define RPM_KEY_UV 0x00007675 /* "uv" */
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#define RPM_KEY_MA 0x0000616d /* "ma" */
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static int rpm_reg_write_active(struct qcom_rpm_reg *vreg,
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struct rpm_regulator_req *req,
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size_t size)
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{
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return qcom_rpm_smd_write(vreg->rpm,
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QCOM_SMD_RPM_ACTIVE_STATE,
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vreg->type,
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vreg->id,
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req, size);
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}
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static int rpm_reg_enable(struct regulator_dev *rdev)
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{
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struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
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struct rpm_regulator_req req;
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int ret;
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req.key = cpu_to_le32(RPM_KEY_SWEN);
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req.nbytes = cpu_to_le32(sizeof(u32));
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req.value = cpu_to_le32(1);
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ret = rpm_reg_write_active(vreg, &req, sizeof(req));
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if (!ret)
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vreg->is_enabled = 1;
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return ret;
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}
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static int rpm_reg_is_enabled(struct regulator_dev *rdev)
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{
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struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
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return vreg->is_enabled;
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}
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static int rpm_reg_disable(struct regulator_dev *rdev)
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{
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struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
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struct rpm_regulator_req req;
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int ret;
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req.key = cpu_to_le32(RPM_KEY_SWEN);
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req.nbytes = cpu_to_le32(sizeof(u32));
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req.value = 0;
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ret = rpm_reg_write_active(vreg, &req, sizeof(req));
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if (!ret)
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vreg->is_enabled = 0;
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return ret;
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}
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static int rpm_reg_get_voltage(struct regulator_dev *rdev)
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{
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struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
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return vreg->uV;
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}
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static int rpm_reg_set_voltage(struct regulator_dev *rdev,
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int min_uV,
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int max_uV,
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unsigned *selector)
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{
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struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
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struct rpm_regulator_req req;
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int ret = 0;
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req.key = cpu_to_le32(RPM_KEY_UV);
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req.nbytes = cpu_to_le32(sizeof(u32));
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req.value = cpu_to_le32(min_uV);
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ret = rpm_reg_write_active(vreg, &req, sizeof(req));
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if (!ret)
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vreg->uV = min_uV;
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return ret;
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}
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static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
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{
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struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
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struct rpm_regulator_req req;
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req.key = cpu_to_le32(RPM_KEY_MA);
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req.nbytes = cpu_to_le32(sizeof(u32));
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req.value = cpu_to_le32(load_uA / 1000);
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return rpm_reg_write_active(vreg, &req, sizeof(req));
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}
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static const struct regulator_ops rpm_smps_ldo_ops = {
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.enable = rpm_reg_enable,
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.disable = rpm_reg_disable,
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.is_enabled = rpm_reg_is_enabled,
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.get_voltage = rpm_reg_get_voltage,
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.set_voltage = rpm_reg_set_voltage,
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.set_load = rpm_reg_set_load,
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};
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static const struct regulator_ops rpm_switch_ops = {
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.enable = rpm_reg_enable,
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.disable = rpm_reg_disable,
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.is_enabled = rpm_reg_is_enabled,
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};
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static const struct regulator_desc pma8084_hfsmps = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
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REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
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},
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.n_linear_ranges = 2,
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.n_voltages = 159,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pma8084_ftsmps = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
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REGULATOR_LINEAR_RANGE(700000, 185, 339, 10000),
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},
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.n_linear_ranges = 2,
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.n_voltages = 340,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pma8084_pldo = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(750000, 0, 30, 25000),
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REGULATOR_LINEAR_RANGE(1500000, 31, 99, 50000),
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},
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.n_linear_ranges = 2,
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.n_voltages = 100,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pma8084_nldo = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
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},
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.n_linear_ranges = 1,
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.n_voltages = 64,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pma8084_switch = {
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.ops = &rpm_switch_ops,
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};
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static const struct regulator_desc pm8x41_hfsmps = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
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REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
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},
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.n_linear_ranges = 2,
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.n_voltages = 159,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pm8841_ftsmps = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
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REGULATOR_LINEAR_RANGE(700000, 185, 339, 10000),
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},
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.n_linear_ranges = 2,
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.n_voltages = 340,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pm8941_boost = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(4000000, 0, 15, 100000),
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},
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.n_linear_ranges = 1,
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.n_voltages = 16,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pm8941_pldo = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE( 750000, 0, 30, 25000),
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REGULATOR_LINEAR_RANGE(1500000, 31, 99, 50000),
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},
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.n_linear_ranges = 2,
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.n_voltages = 100,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pm8941_nldo = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
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},
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.n_linear_ranges = 1,
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.n_voltages = 64,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pm8941_lnldo = {
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.fixed_uV = 1740000,
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.n_voltages = 1,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pm8941_switch = {
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.ops = &rpm_switch_ops,
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};
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static const struct regulator_desc pm8916_pldo = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(750000, 0, 208, 12500),
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},
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.n_linear_ranges = 1,
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.n_voltages = 209,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pm8916_nldo = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
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},
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.n_linear_ranges = 1,
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.n_voltages = 94,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pm8916_buck_lvo_smps = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
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REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000),
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},
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.n_linear_ranges = 2,
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.n_voltages = 128,
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.ops = &rpm_smps_ldo_ops,
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};
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static const struct regulator_desc pm8916_buck_hvo_smps = {
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.linear_ranges = (struct regulator_linear_range[]) {
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REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000),
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},
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.n_linear_ranges = 1,
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.n_voltages = 32,
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.ops = &rpm_smps_ldo_ops,
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};
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struct rpm_regulator_data {
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const char *name;
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u32 type;
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u32 id;
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const struct regulator_desc *desc;
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const char *supply;
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};
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static const struct rpm_regulator_data rpm_pm8841_regulators[] = {
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{ "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" },
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{ "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" },
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{ "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" },
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{ "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" },
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{ "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
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{ "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" },
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{ "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" },
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{ "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" },
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{}
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};
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static const struct rpm_regulator_data rpm_pm8916_regulators[] = {
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{ "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
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{ "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" },
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{ "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" },
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{ "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" },
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{ "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" },
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{ "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" },
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{ "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" },
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{ "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" },
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{ "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" },
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{ "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" },
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{ "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" },
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{ "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
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{ "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
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{ "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
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{ "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
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{ "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
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{ "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
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{ "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
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{ "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
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{ "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
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{ "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
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{ "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
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{}
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};
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static const struct rpm_regulator_data rpm_pm8941_regulators[] = {
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{ "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" },
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{ "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" },
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{ "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" },
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{ "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost },
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{ "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" },
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{ "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" },
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{ "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" },
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{ "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" },
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{ "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" },
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{ "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
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{ "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" },
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{ "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
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{ "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
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{ "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
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{ "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" },
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{ "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
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{ "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
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{ "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
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{ "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
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{ "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
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{ "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
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{ "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
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{ "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
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{ "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
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{ "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" },
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{ "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
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{ "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
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{ "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
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{ "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" },
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|
{ "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" },
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|
{ "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" },
|
|
|
|
{ "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" },
|
|
{ "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" },
|
|
|
|
{}
|
|
};
|
|
|
|
static const struct rpm_regulator_data rpm_pma8084_regulators[] = {
|
|
{ "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" },
|
|
{ "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" },
|
|
{ "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" },
|
|
{ "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" },
|
|
{ "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" },
|
|
{ "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" },
|
|
{ "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" },
|
|
{ "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" },
|
|
{ "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" },
|
|
{ "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" },
|
|
{ "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" },
|
|
{ "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" },
|
|
|
|
{ "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" },
|
|
{ "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
|
|
{ "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
|
|
{ "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
|
|
{ "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" },
|
|
{ "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
|
|
{ "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" },
|
|
{ "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" },
|
|
{ "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
|
|
{ "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
|
|
{ "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" },
|
|
{ "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
|
|
{ "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
|
|
{ "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
|
|
{ "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
|
|
{ "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" },
|
|
{ "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" },
|
|
{ "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" },
|
|
{ "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" },
|
|
{ "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
|
|
{ "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" },
|
|
{ "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" },
|
|
{ "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
|
|
{ "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
|
|
{ "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" },
|
|
{ "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
|
|
{ "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
|
|
|
|
{ "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch },
|
|
{ "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch },
|
|
{ "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch },
|
|
{ "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch },
|
|
{ "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch },
|
|
|
|
{}
|
|
};
|
|
|
|
static const struct of_device_id rpm_of_match[] = {
|
|
{ .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators },
|
|
{ .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators },
|
|
{ .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators },
|
|
{ .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rpm_of_match);
|
|
|
|
static int rpm_reg_probe(struct platform_device *pdev)
|
|
{
|
|
const struct rpm_regulator_data *reg;
|
|
const struct of_device_id *match;
|
|
struct regulator_config config = { };
|
|
struct regulator_dev *rdev;
|
|
struct qcom_rpm_reg *vreg;
|
|
struct qcom_smd_rpm *rpm;
|
|
|
|
rpm = dev_get_drvdata(pdev->dev.parent);
|
|
if (!rpm) {
|
|
dev_err(&pdev->dev, "unable to retrieve handle to rpm\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
match = of_match_device(rpm_of_match, &pdev->dev);
|
|
for (reg = match->data; reg->name; reg++) {
|
|
vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
|
|
if (!vreg)
|
|
return -ENOMEM;
|
|
|
|
vreg->dev = &pdev->dev;
|
|
vreg->type = reg->type;
|
|
vreg->id = reg->id;
|
|
vreg->rpm = rpm;
|
|
|
|
memcpy(&vreg->desc, reg->desc, sizeof(vreg->desc));
|
|
|
|
vreg->desc.id = -1;
|
|
vreg->desc.owner = THIS_MODULE;
|
|
vreg->desc.type = REGULATOR_VOLTAGE;
|
|
vreg->desc.name = reg->name;
|
|
vreg->desc.supply_name = reg->supply;
|
|
vreg->desc.of_match = reg->name;
|
|
|
|
config.dev = &pdev->dev;
|
|
config.driver_data = vreg;
|
|
rdev = devm_regulator_register(&pdev->dev, &vreg->desc, &config);
|
|
if (IS_ERR(rdev)) {
|
|
dev_err(&pdev->dev, "failed to register %s\n", reg->name);
|
|
return PTR_ERR(rdev);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver rpm_reg_driver = {
|
|
.probe = rpm_reg_probe,
|
|
.driver = {
|
|
.name = "qcom_rpm_smd_regulator",
|
|
.of_match_table = rpm_of_match,
|
|
},
|
|
};
|
|
|
|
static int __init rpm_reg_init(void)
|
|
{
|
|
return platform_driver_register(&rpm_reg_driver);
|
|
}
|
|
subsys_initcall(rpm_reg_init);
|
|
|
|
static void __exit rpm_reg_exit(void)
|
|
{
|
|
platform_driver_unregister(&rpm_reg_driver);
|
|
}
|
|
module_exit(rpm_reg_exit)
|
|
|
|
MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
|
|
MODULE_LICENSE("GPL v2");
|