366 строки
10 KiB
C
366 строки
10 KiB
C
/*
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* IDE host driver for AT91 (SAM9, CAP9, AT572D940HF) Static Memory Controller
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* with Compact Flash True IDE logic
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*
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* Copyright (c) 2008, 2009 Kelvatek Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/ide.h>
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#include <linux/platform_device.h>
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#include <mach/board.h>
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#include <mach/gpio.h>
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#include <mach/at91sam9_smc.h>
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#define DRV_NAME "at91_ide"
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#define perr(fmt, args...) pr_err(DRV_NAME ": " fmt, ##args)
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#define pdbg(fmt, args...) pr_debug("%s " fmt, __func__, ##args)
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/*
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* Access to IDE device is possible through EBI Static Memory Controller
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* with Compact Flash logic. For details see EBI and SMC datasheet sections
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* of any microcontroller from AT91SAM9 family.
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*
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* Within SMC chip select address space, lines A[23:21] distinguish Compact
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* Flash modes (I/O, common memory, attribute memory, True IDE). IDE modes are:
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* 0x00c0000 - True IDE
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* 0x00e0000 - Alternate True IDE (Alt Status Register)
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*
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* On True IDE mode Task File and Data Register are mapped at the same address.
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* To distinguish access between these two different bus data width is used:
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* 8Bit for Task File, 16Bit for Data I/O.
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*
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* After initialization we do 8/16 bit flipping (changes in SMC MODE register)
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* only inside IDE callback routines which are serialized by IDE layer,
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* so no additional locking needed.
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*/
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#define TASK_FILE 0x00c00000
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#define ALT_MODE 0x00e00000
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#define REGS_SIZE 8
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#define enter_16bit(cs, mode) do { \
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mode = at91_sys_read(AT91_SMC_MODE(cs)); \
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at91_sys_write(AT91_SMC_MODE(cs), mode | AT91_SMC_DBW_16); \
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} while (0)
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#define leave_16bit(cs, mode) at91_sys_write(AT91_SMC_MODE(cs), mode);
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static void set_smc_timings(const u8 chipselect, const u16 cycle,
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const u16 setup, const u16 pulse,
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const u16 data_float, int use_iordy)
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{
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unsigned long mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_BAT_SELECT;
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/* disable or enable waiting for IORDY signal */
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if (use_iordy)
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mode |= AT91_SMC_EXNWMODE_READY;
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/* add data float cycles if needed */
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if (data_float)
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mode |= AT91_SMC_TDF_(data_float);
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at91_sys_write(AT91_SMC_MODE(chipselect), mode);
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/* setup timings in SMC */
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at91_sys_write(AT91_SMC_SETUP(chipselect), AT91_SMC_NWESETUP_(setup) |
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AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(setup) |
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AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(chipselect), AT91_SMC_NWEPULSE_(pulse) |
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AT91_SMC_NCS_WRPULSE_(cycle) |
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AT91_SMC_NRDPULSE_(pulse) |
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AT91_SMC_NCS_RDPULSE_(cycle));
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at91_sys_write(AT91_SMC_CYCLE(chipselect), AT91_SMC_NWECYCLE_(cycle) |
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AT91_SMC_NRDCYCLE_(cycle));
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}
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static unsigned int calc_mck_cycles(unsigned int ns, unsigned int mck_hz)
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{
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u64 tmp = ns;
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tmp *= mck_hz;
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tmp += 1000*1000*1000 - 1; /* round up */
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do_div(tmp, 1000*1000*1000);
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return (unsigned int) tmp;
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}
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static void apply_timings(const u8 chipselect, const u8 pio,
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const struct ide_timing *timing, int use_iordy)
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{
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unsigned int t0, t1, t2, t6z;
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unsigned int cycle, setup, pulse, data_float;
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unsigned int mck_hz;
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struct clk *mck;
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/* see table 22 of Compact Flash standard 4.1 for the meaning,
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* we do not stretch active (t2) time, so setup (t1) + hold time (th)
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* assure at least minimal recovery (t2i) time */
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t0 = timing->cyc8b;
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t1 = timing->setup;
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t2 = timing->act8b;
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t6z = (pio < 5) ? 30 : 20;
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pdbg("t0=%u t1=%u t2=%u t6z=%u\n", t0, t1, t2, t6z);
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mck = clk_get(NULL, "mck");
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BUG_ON(IS_ERR(mck));
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mck_hz = clk_get_rate(mck);
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pdbg("mck_hz=%u\n", mck_hz);
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cycle = calc_mck_cycles(t0, mck_hz);
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setup = calc_mck_cycles(t1, mck_hz);
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pulse = calc_mck_cycles(t2, mck_hz);
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data_float = calc_mck_cycles(t6z, mck_hz);
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pdbg("cycle=%u setup=%u pulse=%u data_float=%u\n",
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cycle, setup, pulse, data_float);
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set_smc_timings(chipselect, cycle, setup, pulse, data_float, use_iordy);
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}
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static void at91_ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
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void *buf, unsigned int len)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct ide_io_ports *io_ports = &hwif->io_ports;
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u8 chipselect = hwif->select_data;
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unsigned long mode;
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pdbg("cs %u buf %p len %d\n", chipselect, buf, len);
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len++;
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enter_16bit(chipselect, mode);
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readsw((void __iomem *)io_ports->data_addr, buf, len / 2);
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leave_16bit(chipselect, mode);
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}
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static void at91_ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
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void *buf, unsigned int len)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct ide_io_ports *io_ports = &hwif->io_ports;
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u8 chipselect = hwif->select_data;
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unsigned long mode;
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pdbg("cs %u buf %p len %d\n", chipselect, buf, len);
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enter_16bit(chipselect, mode);
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writesw((void __iomem *)io_ports->data_addr, buf, len / 2);
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leave_16bit(chipselect, mode);
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}
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static void at91_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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struct ide_timing *timing;
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u8 chipselect = drive->hwif->select_data;
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int use_iordy = 0;
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pdbg("chipselect %u pio %u\n", chipselect, pio);
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timing = ide_timing_find_mode(XFER_PIO_0 + pio);
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BUG_ON(!timing);
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if (ide_pio_need_iordy(drive, pio))
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use_iordy = 1;
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apply_timings(chipselect, pio, timing, use_iordy);
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}
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static const struct ide_tp_ops at91_ide_tp_ops = {
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.exec_command = ide_exec_command,
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.read_status = ide_read_status,
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.read_altstatus = ide_read_altstatus,
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.write_devctl = ide_write_devctl,
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.dev_select = ide_dev_select,
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.tf_load = ide_tf_load,
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.tf_read = ide_tf_read,
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.input_data = at91_ide_input_data,
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.output_data = at91_ide_output_data,
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};
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static const struct ide_port_ops at91_ide_port_ops = {
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.set_pio_mode = at91_ide_set_pio_mode,
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};
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static const struct ide_port_info at91_ide_port_info __initdata = {
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.port_ops = &at91_ide_port_ops,
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.tp_ops = &at91_ide_tp_ops,
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.host_flags = IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA | IDE_HFLAG_SINGLE |
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IDE_HFLAG_NO_IO_32BIT | IDE_HFLAG_UNMASK_IRQS,
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.pio_mask = ATA_PIO6,
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.chipset = ide_generic,
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};
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/*
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* If interrupt is delivered through GPIO, IRQ are triggered on falling
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* and rising edge of signal. Whereas IDE device request interrupt on high
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* level (rising edge in our case). This mean we have fake interrupts, so
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* we need to check interrupt pin and exit instantly from ISR when line
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* is on low level.
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*/
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irqreturn_t at91_irq_handler(int irq, void *dev_id)
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{
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int ntries = 8;
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int pin_val1, pin_val2;
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/* additional deglitch, line can be noisy in badly designed PCB */
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do {
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pin_val1 = at91_get_gpio_value(irq);
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pin_val2 = at91_get_gpio_value(irq);
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} while (pin_val1 != pin_val2 && --ntries > 0);
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if (pin_val1 == 0 || ntries <= 0)
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return IRQ_HANDLED;
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return ide_intr(irq, dev_id);
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}
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static int __init at91_ide_probe(struct platform_device *pdev)
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{
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int ret;
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struct ide_hw hw, *hws[] = { &hw };
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struct ide_host *host;
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struct resource *res;
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unsigned long tf_base = 0, ctl_base = 0;
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struct at91_cf_data *board = pdev->dev.platform_data;
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if (!board)
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return -ENODEV;
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if (board->det_pin && at91_get_gpio_value(board->det_pin) != 0) {
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perr("no device detected\n");
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return -ENODEV;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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perr("can't get memory resource\n");
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return -ENODEV;
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}
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if (!devm_request_mem_region(&pdev->dev, res->start + TASK_FILE,
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REGS_SIZE, "ide") ||
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!devm_request_mem_region(&pdev->dev, res->start + ALT_MODE,
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REGS_SIZE, "alt")) {
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perr("memory resources in use\n");
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return -EBUSY;
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}
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pdbg("chipselect %u irq %u res %08lx\n", board->chipselect,
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board->irq_pin, (unsigned long) res->start);
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tf_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + TASK_FILE,
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REGS_SIZE);
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ctl_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + ALT_MODE,
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REGS_SIZE);
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if (!tf_base || !ctl_base) {
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perr("can't map memory regions\n");
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return -EBUSY;
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}
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memset(&hw, 0, sizeof(hw));
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if (board->flags & AT91_IDE_SWAP_A0_A2) {
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/* workaround for stupid hardware bug */
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hw.io_ports.data_addr = tf_base + 0;
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hw.io_ports.error_addr = tf_base + 4;
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hw.io_ports.nsect_addr = tf_base + 2;
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hw.io_ports.lbal_addr = tf_base + 6;
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hw.io_ports.lbam_addr = tf_base + 1;
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hw.io_ports.lbah_addr = tf_base + 5;
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hw.io_ports.device_addr = tf_base + 3;
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hw.io_ports.command_addr = tf_base + 7;
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hw.io_ports.ctl_addr = ctl_base + 3;
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} else
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ide_std_init_ports(&hw, tf_base, ctl_base + 6);
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hw.irq = board->irq_pin;
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hw.dev = &pdev->dev;
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host = ide_host_alloc(&at91_ide_port_info, hws, 1);
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if (!host) {
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perr("failed to allocate ide host\n");
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return -ENOMEM;
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}
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/* setup Static Memory Controller - PIO 0 as default */
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apply_timings(board->chipselect, 0, ide_timing_find_mode(XFER_PIO_0), 0);
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/* with GPIO interrupt we have to do quirks in handler */
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if (board->irq_pin >= PIN_BASE)
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host->irq_handler = at91_irq_handler;
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host->ports[0]->select_data = board->chipselect;
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ret = ide_host_register(host, &at91_ide_port_info, hws);
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if (ret) {
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perr("failed to register ide host\n");
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goto err_free_host;
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}
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platform_set_drvdata(pdev, host);
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return 0;
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err_free_host:
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ide_host_free(host);
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return ret;
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}
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static int __exit at91_ide_remove(struct platform_device *pdev)
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{
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struct ide_host *host = platform_get_drvdata(pdev);
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ide_host_remove(host);
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return 0;
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}
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static struct platform_driver at91_ide_driver = {
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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.remove = __exit_p(at91_ide_remove),
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};
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static int __init at91_ide_init(void)
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{
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return platform_driver_probe(&at91_ide_driver, at91_ide_probe);
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}
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static void __exit at91_ide_exit(void)
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{
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platform_driver_unregister(&at91_ide_driver);
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}
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module_init(at91_ide_init);
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module_exit(at91_ide_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Stanislaw Gruszka <stf_xl@wp.pl>");
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