ba5bf51acf
The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready for image processing. Please refer to PG232 for details. The CSI2 Rx controller filters out all packets except for the packets with data type fixed in hardware. RAW8 packets are always allowed to pass through. It is also used to setup and handle interrupts and enable the core. It logs all the events in respective counters between streaming on and off. The driver supports only the video format bridge enabled configuration. Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the CSI v2.0 feature is enabled in design. When the VCX feature is enabled, the maximum number of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| xilinx-csi2rxss.c | ||
| xilinx-dma.c | ||
| xilinx-dma.h | ||
| xilinx-tpg.c | ||
| xilinx-vip.c | ||
| xilinx-vip.h | ||
| xilinx-vipp.c | ||
| xilinx-vipp.h | ||
| xilinx-vtc.c | ||
| xilinx-vtc.h | ||