Zong Li 38f5bd23de riscv: Add cache information in AUX vector ... There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. Currently, AT_L1I_X, AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall could use them to get information of cache through AUX vector. The result of 'getconf -a' as follows: LEVEL1_ICACHE_SIZE 32768 LEVEL1_ICACHE_ASSOC 8 LEVEL1_ICACHE_LINESIZE 64 LEVEL1_DCACHE_SIZE 32768 LEVEL1_DCACHE_ASSOC 8 LEVEL1_DCACHE_LINESIZE 64 LEVEL2_CACHE_SIZE 2097152 LEVEL2_CACHE_ASSOC 32 LEVEL2_CACHE_LINESIZE 64 Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Pekka Enberg <penberg@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-09-15 18:46:08 -07:00
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Kbuild	treewide: Add SPDX license identifier - Kbuild	2019-05-30 11:32:33 -07:00
auxvec.h	riscv: Add cache information in AUX vector	2020-09-15 18:46:08 -07:00
bitsperlong.h	treewide: add "WITH Linux-syscall-note" to SPDX tag of uapi headers	2019-07-25 11:05:10 +02:00
bpf_perf_event.h	riscv, bpf: Add missing uapi header for BPF_PROG_TYPE_PERF_EVENT programs	2019-12-19 16:03:31 +01:00
byteorder.h	treewide: add "WITH Linux-syscall-note" to SPDX tag of uapi headers	2019-07-25 11:05:10 +02:00
elf.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
hwcap.h	riscv: Fix typo in asm/hwcap.h uapi header	2020-07-30 11:37:38 -07:00
perf_regs.h	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00
ptrace.h	treewide: add "WITH Linux-syscall-note" to SPDX tag of uapi headers	2019-07-25 11:05:10 +02:00
sigcontext.h	treewide: add "WITH Linux-syscall-note" to SPDX tag of uapi headers	2019-07-25 11:05:10 +02:00
ucontext.h	riscv: clean up the macro format in each header file	2019-11-12 12:04:52 -08:00
unistd.h	Replace HTTP links with HTTPS ones: RISC-V	2020-07-30 11:37:40 -07:00