429 строки
12 KiB
C
429 строки
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* pci-rcar-gen2: internal PCI bus support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Cogent Embedded, Inc.
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*
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* Author: Valentine Barshak <valentine.barshak@cogentembedded.com>
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include "../pci.h"
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/* AHB-PCI Bridge PCI communication registers */
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#define RCAR_AHBPCI_PCICOM_OFFSET 0x800
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#define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
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#define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
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#define RCAR_PCIAHB_PREFETCH0 0x0
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#define RCAR_PCIAHB_PREFETCH4 0x1
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#define RCAR_PCIAHB_PREFETCH8 0x2
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#define RCAR_PCIAHB_PREFETCH16 0x3
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#define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
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#define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
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#define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
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#define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
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#define RCAR_AHBPCI_WIN1_HOST (1 << 30)
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#define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
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#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
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#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
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#define RCAR_PCI_INT_SIGTABORT (1 << 0)
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#define RCAR_PCI_INT_SIGRETABORT (1 << 1)
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#define RCAR_PCI_INT_REMABORT (1 << 2)
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#define RCAR_PCI_INT_PERR (1 << 3)
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#define RCAR_PCI_INT_SIGSERR (1 << 4)
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#define RCAR_PCI_INT_RESERR (1 << 5)
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#define RCAR_PCI_INT_WIN1ERR (1 << 12)
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#define RCAR_PCI_INT_WIN2ERR (1 << 13)
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#define RCAR_PCI_INT_A (1 << 16)
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#define RCAR_PCI_INT_B (1 << 17)
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#define RCAR_PCI_INT_PME (1 << 19)
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#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
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RCAR_PCI_INT_SIGRETABORT | \
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RCAR_PCI_INT_REMABORT | \
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RCAR_PCI_INT_PERR | \
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RCAR_PCI_INT_SIGSERR | \
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RCAR_PCI_INT_RESERR | \
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RCAR_PCI_INT_WIN1ERR | \
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RCAR_PCI_INT_WIN2ERR)
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#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
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#define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
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#define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
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#define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
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#define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
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#define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
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#define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
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RCAR_AHB_BUS_MMODE_BYTE_BURST | \
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RCAR_AHB_BUS_MMODE_WR_INCR | \
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RCAR_AHB_BUS_MMODE_HBUS_REQ | \
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RCAR_AHB_BUS_SMODE_READYCTR)
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#define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
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#define RCAR_USBCTR_USBH_RST (1 << 0)
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#define RCAR_USBCTR_PCICLK_MASK (1 << 1)
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#define RCAR_USBCTR_PLL_RST (1 << 2)
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#define RCAR_USBCTR_DIRPD (1 << 8)
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#define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
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#define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
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#define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
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#define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
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#define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
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#define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
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#define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
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#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
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struct rcar_pci_priv {
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struct device *dev;
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void __iomem *reg;
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struct resource mem_res;
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struct resource *cfg_res;
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unsigned busnr;
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int irq;
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unsigned long window_size;
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unsigned long window_addr;
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unsigned long window_pci;
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};
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/* PCI configuration space operations */
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static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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struct pci_sys_data *sys = bus->sysdata;
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struct rcar_pci_priv *priv = sys->private_data;
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int slot, val;
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if (sys->busnr != bus->number || PCI_FUNC(devfn))
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return NULL;
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/* Only one EHCI/OHCI device built-in */
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slot = PCI_SLOT(devfn);
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if (slot > 2)
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return NULL;
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/* bridge logic only has registers to 0x40 */
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if (slot == 0x0 && where >= 0x40)
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return NULL;
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val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
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RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
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iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
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return priv->reg + (slot >> 1) * 0x100 + where;
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}
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/* PCI interrupt mapping */
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static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct pci_sys_data *sys = dev->bus->sysdata;
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struct rcar_pci_priv *priv = sys->private_data;
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int irq;
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irq = of_irq_parse_and_map_pci(dev, slot, pin);
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if (!irq)
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irq = priv->irq;
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return irq;
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}
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#ifdef CONFIG_PCI_DEBUG
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/* if debug enabled, then attach an error handler irq to the bridge */
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static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
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{
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struct rcar_pci_priv *priv = pw;
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struct device *dev = priv->dev;
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u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
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if (status & RCAR_PCI_INT_ALLERRORS) {
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dev_err(dev, "error irq: status %08x\n", status);
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/* clear the error(s) */
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iowrite32(status & RCAR_PCI_INT_ALLERRORS,
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priv->reg + RCAR_PCI_INT_STATUS_REG);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
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{
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struct device *dev = priv->dev;
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int ret;
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u32 val;
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ret = devm_request_irq(dev, priv->irq, rcar_pci_err_irq,
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IRQF_SHARED, "error irq", priv);
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if (ret) {
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dev_err(dev, "cannot claim IRQ for error handling\n");
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return;
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}
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val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
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val |= RCAR_PCI_INT_ALLERRORS;
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iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
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}
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#else
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static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
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#endif
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/* PCI host controller setup */
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static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
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{
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struct rcar_pci_priv *priv = sys->private_data;
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struct device *dev = priv->dev;
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void __iomem *reg = priv->reg;
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u32 val;
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int ret;
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pm_runtime_enable(dev);
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pm_runtime_get_sync(dev);
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val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
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dev_info(dev, "PCI: bus%u revision %x\n", sys->busnr, val);
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/* Disable Direct Power Down State and assert reset */
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val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
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val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
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iowrite32(val, reg + RCAR_USBCTR_REG);
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udelay(4);
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/* De-assert reset and reset PCIAHB window1 size */
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val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
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RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
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/* Setup PCIAHB window1 size */
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switch (priv->window_size) {
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case SZ_2G:
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val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
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break;
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case SZ_1G:
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val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
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break;
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case SZ_512M:
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val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
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break;
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default:
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pr_warn("unknown window size %ld - defaulting to 256M\n",
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priv->window_size);
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priv->window_size = SZ_256M;
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/* fall-through */
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case SZ_256M:
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val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
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break;
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}
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iowrite32(val, reg + RCAR_USBCTR_REG);
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/* Configure AHB master and slave modes */
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iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
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/* Configure PCI arbiter */
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val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
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val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
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RCAR_PCI_ARBITER_PCIBP_MODE;
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iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
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/* PCI-AHB mapping */
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iowrite32(priv->window_addr | RCAR_PCIAHB_PREFETCH16,
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reg + RCAR_PCIAHB_WIN1_CTR_REG);
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/* AHB-PCI mapping: OHCI/EHCI registers */
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val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
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iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
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/* Enable AHB-PCI bridge PCI configuration access */
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iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
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reg + RCAR_AHBPCI_WIN1_CTR_REG);
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/* Set PCI-AHB Window1 address */
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iowrite32(priv->window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH,
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reg + PCI_BASE_ADDRESS_1);
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/* Set AHB-PCI bridge PCI communication area address */
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val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
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iowrite32(val, reg + PCI_BASE_ADDRESS_0);
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val = ioread32(reg + PCI_COMMAND);
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val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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iowrite32(val, reg + PCI_COMMAND);
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/* Enable PCI interrupts */
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iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
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reg + RCAR_PCI_INT_ENABLE_REG);
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if (priv->irq > 0)
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rcar_pci_setup_errirq(priv);
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/* Add PCI resources */
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pci_add_resource(&sys->resources, &priv->mem_res);
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ret = devm_request_pci_bus_resources(dev, &sys->resources);
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if (ret < 0)
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return ret;
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/* Setup bus number based on platform device id / of bus-range */
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sys->busnr = priv->busnr;
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return 1;
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}
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static struct pci_ops rcar_pci_ops = {
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.map_bus = rcar_pci_cfg_base,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
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struct device_node *np)
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{
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struct device *dev = pci->dev;
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struct of_pci_range range;
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struct of_pci_range_parser parser;
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int index = 0;
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/* Failure to parse is ok as we fall back to defaults */
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if (of_pci_dma_range_parser_init(&parser, np))
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return 0;
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/* Get the dma-ranges from DT */
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for_each_of_pci_range(&parser, &range) {
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/* Hardware only allows one inbound 32-bit range */
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if (index)
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return -EINVAL;
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pci->window_addr = (unsigned long)range.cpu_addr;
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pci->window_pci = (unsigned long)range.pci_addr;
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pci->window_size = (unsigned long)range.size;
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/* Catch HW limitations */
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if (!(range.flags & IORESOURCE_PREFETCH)) {
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dev_err(dev, "window must be prefetchable\n");
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return -EINVAL;
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}
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if (pci->window_addr) {
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u32 lowaddr = 1 << (ffs(pci->window_addr) - 1);
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if (lowaddr < pci->window_size) {
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dev_err(dev, "invalid window size/addr\n");
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return -EINVAL;
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}
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}
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index++;
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}
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return 0;
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}
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static int rcar_pci_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *cfg_res, *mem_res;
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struct rcar_pci_priv *priv;
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void __iomem *reg;
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struct hw_pci hw;
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void *hw_private[1];
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cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(dev, cfg_res);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!mem_res || !mem_res->start)
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return -ENODEV;
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if (mem_res->start & 0xFFFF)
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return -EINVAL;
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priv = devm_kzalloc(dev, sizeof(struct rcar_pci_priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->mem_res = *mem_res;
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priv->cfg_res = cfg_res;
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priv->irq = platform_get_irq(pdev, 0);
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priv->reg = reg;
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priv->dev = dev;
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if (priv->irq < 0) {
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dev_err(dev, "no valid irq found\n");
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return priv->irq;
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}
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/* default window addr and size if not specified in DT */
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priv->window_addr = 0x40000000;
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priv->window_pci = 0x40000000;
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priv->window_size = SZ_1G;
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if (dev->of_node) {
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struct resource busnr;
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int ret;
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ret = of_pci_parse_bus_range(dev->of_node, &busnr);
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if (ret < 0) {
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dev_err(dev, "failed to parse bus-range\n");
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return ret;
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}
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priv->busnr = busnr.start;
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if (busnr.end != busnr.start)
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dev_warn(dev, "only one bus number supported\n");
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ret = rcar_pci_parse_map_dma_ranges(priv, dev->of_node);
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if (ret < 0) {
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dev_err(dev, "failed to parse dma-range\n");
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return ret;
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}
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} else {
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priv->busnr = pdev->id;
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}
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hw_private[0] = priv;
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memset(&hw, 0, sizeof(hw));
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hw.nr_controllers = ARRAY_SIZE(hw_private);
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hw.io_optional = 1;
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hw.private_data = hw_private;
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hw.map_irq = rcar_pci_map_irq;
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hw.ops = &rcar_pci_ops;
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hw.setup = rcar_pci_setup;
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pci_common_init_dev(dev, &hw);
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return 0;
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}
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static const struct of_device_id rcar_pci_of_match[] = {
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{ .compatible = "renesas,pci-r8a7790", },
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{ .compatible = "renesas,pci-r8a7791", },
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{ .compatible = "renesas,pci-r8a7794", },
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{ .compatible = "renesas,pci-rcar-gen2", },
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{ },
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};
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static struct platform_driver rcar_pci_driver = {
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.driver = {
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.name = "pci-rcar-gen2",
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.suppress_bind_attrs = true,
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.of_match_table = rcar_pci_of_match,
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},
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.probe = rcar_pci_probe,
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};
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builtin_platform_driver(rcar_pci_driver);
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