243 строки
7.1 KiB
C
243 строки
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* CQHCI crypto engine (inline encryption) support
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*
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* Copyright 2020 Google LLC
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*/
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#include <linux/blk-crypto.h>
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#include <linux/keyslot-manager.h>
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#include <linux/mmc/host.h>
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#include "cqhci-crypto.h"
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/* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */
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static const struct cqhci_crypto_alg_entry {
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enum cqhci_crypto_alg alg;
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enum cqhci_crypto_key_size key_size;
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} cqhci_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
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[BLK_ENCRYPTION_MODE_AES_256_XTS] = {
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.alg = CQHCI_CRYPTO_ALG_AES_XTS,
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.key_size = CQHCI_CRYPTO_KEY_SIZE_256,
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},
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};
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static inline struct cqhci_host *
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cqhci_host_from_ksm(struct blk_keyslot_manager *ksm)
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{
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struct mmc_host *mmc = container_of(ksm, struct mmc_host, ksm);
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return mmc->cqe_private;
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}
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static int cqhci_crypto_program_key(struct cqhci_host *cq_host,
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const union cqhci_crypto_cfg_entry *cfg,
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int slot)
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{
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u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg);
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int i;
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if (cq_host->ops->program_key)
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return cq_host->ops->program_key(cq_host, cfg, slot);
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/* Clear CFGE */
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cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
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/* Write the key */
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for (i = 0; i < 16; i++) {
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cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[i]),
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slot_offset + i * sizeof(cfg->reg_val[0]));
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}
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/* Write dword 17 */
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cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[17]),
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slot_offset + 17 * sizeof(cfg->reg_val[0]));
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/* Write dword 16, which includes the new value of CFGE */
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cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]),
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slot_offset + 16 * sizeof(cfg->reg_val[0]));
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return 0;
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}
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static int cqhci_crypto_keyslot_program(struct blk_keyslot_manager *ksm,
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const struct blk_crypto_key *key,
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unsigned int slot)
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{
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struct cqhci_host *cq_host = cqhci_host_from_ksm(ksm);
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const union cqhci_crypto_cap_entry *ccap_array =
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cq_host->crypto_cap_array;
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const struct cqhci_crypto_alg_entry *alg =
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&cqhci_crypto_algs[key->crypto_cfg.crypto_mode];
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u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;
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int i;
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int cap_idx = -1;
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union cqhci_crypto_cfg_entry cfg = {};
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int err;
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BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
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for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) {
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if (ccap_array[i].algorithm_id == alg->alg &&
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ccap_array[i].key_size == alg->key_size &&
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(ccap_array[i].sdus_mask & data_unit_mask)) {
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cap_idx = i;
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break;
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}
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}
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if (WARN_ON(cap_idx < 0))
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return -EOPNOTSUPP;
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cfg.data_unit_size = data_unit_mask;
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cfg.crypto_cap_idx = cap_idx;
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cfg.config_enable = CQHCI_CRYPTO_CONFIGURATION_ENABLE;
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if (ccap_array[cap_idx].algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS) {
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/* In XTS mode, the blk_crypto_key's size is already doubled */
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memcpy(cfg.crypto_key, key->raw, key->size/2);
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memcpy(cfg.crypto_key + CQHCI_CRYPTO_KEY_MAX_SIZE/2,
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key->raw + key->size/2, key->size/2);
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} else {
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memcpy(cfg.crypto_key, key->raw, key->size);
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}
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err = cqhci_crypto_program_key(cq_host, &cfg, slot);
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memzero_explicit(&cfg, sizeof(cfg));
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return err;
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}
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static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
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{
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/*
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* Clear the crypto cfg on the device. Clearing CFGE
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* might not be sufficient, so just clear the entire cfg.
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*/
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union cqhci_crypto_cfg_entry cfg = {};
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return cqhci_crypto_program_key(cq_host, &cfg, slot);
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}
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static int cqhci_crypto_keyslot_evict(struct blk_keyslot_manager *ksm,
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const struct blk_crypto_key *key,
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unsigned int slot)
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{
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struct cqhci_host *cq_host = cqhci_host_from_ksm(ksm);
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return cqhci_crypto_clear_keyslot(cq_host, slot);
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}
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/*
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* The keyslot management operations for CQHCI crypto.
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*
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* Note that the block layer ensures that these are never called while the host
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* controller is runtime-suspended. However, the CQE won't necessarily be
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* "enabled" when these are called, i.e. CQHCI_ENABLE might not be set in the
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* CQHCI_CFG register. But the hardware allows that.
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*/
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static const struct blk_ksm_ll_ops cqhci_ksm_ops = {
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.keyslot_program = cqhci_crypto_keyslot_program,
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.keyslot_evict = cqhci_crypto_keyslot_evict,
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};
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static enum blk_crypto_mode_num
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cqhci_find_blk_crypto_mode(union cqhci_crypto_cap_entry cap)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(cqhci_crypto_algs); i++) {
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BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
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if (cqhci_crypto_algs[i].alg == cap.algorithm_id &&
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cqhci_crypto_algs[i].key_size == cap.key_size)
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return i;
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}
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return BLK_ENCRYPTION_MODE_INVALID;
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}
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/**
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* cqhci_crypto_init - initialize CQHCI crypto support
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* @cq_host: a cqhci host
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*
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* If the driver previously set MMC_CAP2_CRYPTO and the CQE declares
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* CQHCI_CAP_CS, initialize the crypto support. This involves reading the
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* crypto capability registers, initializing the keyslot manager, clearing all
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* keyslots, and enabling 128-bit task descriptors.
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*
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* Return: 0 if crypto was initialized or isn't supported; whether
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* MMC_CAP2_CRYPTO remains set indicates which one of those cases it is.
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* Also can return a negative errno value on unexpected error.
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*/
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int cqhci_crypto_init(struct cqhci_host *cq_host)
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{
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struct mmc_host *mmc = cq_host->mmc;
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struct device *dev = mmc_dev(mmc);
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struct blk_keyslot_manager *ksm = &mmc->ksm;
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unsigned int num_keyslots;
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unsigned int cap_idx;
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enum blk_crypto_mode_num blk_mode_num;
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unsigned int slot;
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int err = 0;
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if (!(mmc->caps2 & MMC_CAP2_CRYPTO) ||
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!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
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goto out;
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cq_host->crypto_capabilities.reg_val =
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cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
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cq_host->crypto_cfg_register =
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(u32)cq_host->crypto_capabilities.config_array_ptr * 0x100;
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cq_host->crypto_cap_array =
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devm_kcalloc(dev, cq_host->crypto_capabilities.num_crypto_cap,
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sizeof(cq_host->crypto_cap_array[0]), GFP_KERNEL);
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if (!cq_host->crypto_cap_array) {
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err = -ENOMEM;
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goto out;
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}
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/*
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* CCAP.CFGC is off by one, so the actual number of crypto
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* configurations (a.k.a. keyslots) is CCAP.CFGC + 1.
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*/
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num_keyslots = cq_host->crypto_capabilities.config_count + 1;
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err = devm_blk_ksm_init(dev, ksm, num_keyslots);
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if (err)
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goto out;
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ksm->ksm_ll_ops = cqhci_ksm_ops;
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ksm->dev = dev;
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/* Unfortunately, CQHCI crypto only supports 32 DUN bits. */
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ksm->max_dun_bytes_supported = 4;
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/*
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* Cache all the crypto capabilities and advertise the supported crypto
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* modes and data unit sizes to the block layer.
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*/
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for (cap_idx = 0; cap_idx < cq_host->crypto_capabilities.num_crypto_cap;
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cap_idx++) {
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cq_host->crypto_cap_array[cap_idx].reg_val =
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cpu_to_le32(cqhci_readl(cq_host,
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CQHCI_CRYPTOCAP +
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cap_idx * sizeof(__le32)));
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blk_mode_num = cqhci_find_blk_crypto_mode(
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cq_host->crypto_cap_array[cap_idx]);
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if (blk_mode_num == BLK_ENCRYPTION_MODE_INVALID)
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continue;
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ksm->crypto_modes_supported[blk_mode_num] |=
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cq_host->crypto_cap_array[cap_idx].sdus_mask * 512;
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}
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/* Clear all the keyslots so that we start in a known state. */
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for (slot = 0; slot < num_keyslots; slot++)
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cqhci_crypto_clear_keyslot(cq_host, slot);
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/* CQHCI crypto requires the use of 128-bit task descriptors. */
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cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
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return 0;
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out:
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mmc->caps2 &= ~MMC_CAP2_CRYPTO;
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return err;
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}
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