376 строки
9.1 KiB
C
376 строки
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
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* programmed to go from @count to @limit and optionally interrupt.
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* We've designated TIMER0 for clockevents and TIMER1 for clocksource
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*
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* ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
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* which are suitable for UP and SMP based clocksources respectively
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*/
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#include <linux/interrupt.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <soc/arc/timers.h>
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#include <soc/arc/mcip.h>
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static unsigned long arc_timer_freq;
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static int noinline arc_get_timer_clk(struct device_node *node)
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{
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struct clk *clk;
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int ret;
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("timer missing clk\n");
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Couldn't enable parent clk\n");
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return ret;
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}
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arc_timer_freq = clk_get_rate(clk);
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return 0;
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}
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/********** Clock Source Device *********/
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#ifdef CONFIG_ARC_TIMERS_64BIT
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static u64 arc_read_gfrc(struct clocksource *cs)
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{
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unsigned long flags;
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u32 l, h;
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/*
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* From a programming model pov, there seems to be just one instance of
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* MCIP_CMD/MCIP_READBACK however micro-architecturally there's
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* an instance PER ARC CORE (not per cluster), and there are dedicated
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* hardware decode logic (per core) inside ARConnect to handle
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* simultaneous read/write accesses from cores via those two registers.
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* So several concurrent commands to ARConnect are OK if they are
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* trying to access two different sub-components (like GFRC,
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* inter-core interrupt, etc...). HW also supports simultaneously
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* accessing GFRC by multiple cores.
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* That's why it is safe to disable hard interrupts on the local CPU
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* before access to GFRC instead of taking global MCIP spinlock
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* defined in arch/arc/kernel/mcip.c
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*/
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local_irq_save(flags);
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__mcip_cmd(CMD_GFRC_READ_LO, 0);
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l = read_aux_reg(ARC_REG_MCIP_READBACK);
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__mcip_cmd(CMD_GFRC_READ_HI, 0);
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h = read_aux_reg(ARC_REG_MCIP_READBACK);
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local_irq_restore(flags);
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return (((u64)h) << 32) | l;
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}
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static notrace u64 arc_gfrc_clock_read(void)
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{
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return arc_read_gfrc(NULL);
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}
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static struct clocksource arc_counter_gfrc = {
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.name = "ARConnect GFRC",
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.rating = 400,
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.read = arc_read_gfrc,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init arc_cs_setup_gfrc(struct device_node *node)
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{
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struct mcip_bcr mp;
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int ret;
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READ_BCR(ARC_REG_MCIP_BCR, mp);
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if (!mp.gfrc) {
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pr_warn("Global-64-bit-Ctr clocksource not detected\n");
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return -ENXIO;
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}
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ret = arc_get_timer_clk(node);
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if (ret)
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return ret;
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sched_clock_register(arc_gfrc_clock_read, 64, arc_timer_freq);
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return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
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}
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TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
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#define AUX_RTC_CTRL 0x103
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#define AUX_RTC_LOW 0x104
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#define AUX_RTC_HIGH 0x105
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static u64 arc_read_rtc(struct clocksource *cs)
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{
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unsigned long status;
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u32 l, h;
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/*
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* hardware has an internal state machine which tracks readout of
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* low/high and updates the CTRL.status if
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* - interrupt/exception taken between the two reads
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* - high increments after low has been read
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*/
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do {
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l = read_aux_reg(AUX_RTC_LOW);
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h = read_aux_reg(AUX_RTC_HIGH);
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status = read_aux_reg(AUX_RTC_CTRL);
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} while (!(status & BIT(31)));
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return (((u64)h) << 32) | l;
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}
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static notrace u64 arc_rtc_clock_read(void)
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{
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return arc_read_rtc(NULL);
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}
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static struct clocksource arc_counter_rtc = {
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.name = "ARCv2 RTC",
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.rating = 350,
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.read = arc_read_rtc,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init arc_cs_setup_rtc(struct device_node *node)
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{
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struct bcr_timer timer;
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int ret;
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READ_BCR(ARC_REG_TIMERS_BCR, timer);
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if (!timer.rtc) {
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pr_warn("Local-64-bit-Ctr clocksource not detected\n");
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return -ENXIO;
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}
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/* Local to CPU hence not usable in SMP */
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if (IS_ENABLED(CONFIG_SMP)) {
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pr_warn("Local-64-bit-Ctr not usable in SMP\n");
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return -EINVAL;
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}
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ret = arc_get_timer_clk(node);
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if (ret)
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return ret;
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write_aux_reg(AUX_RTC_CTRL, 1);
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sched_clock_register(arc_rtc_clock_read, 64, arc_timer_freq);
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return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
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}
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TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
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#endif
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/*
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* 32bit TIMER1 to keep counting monotonically and wraparound
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*/
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static u64 arc_read_timer1(struct clocksource *cs)
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{
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return (u64) read_aux_reg(ARC_REG_TIMER1_CNT);
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}
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static notrace u64 arc_timer1_clock_read(void)
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{
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return arc_read_timer1(NULL);
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}
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static struct clocksource arc_counter_timer1 = {
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.name = "ARC Timer1",
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.rating = 300,
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.read = arc_read_timer1,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init arc_cs_setup_timer1(struct device_node *node)
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{
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int ret;
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/* Local to CPU hence not usable in SMP */
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if (IS_ENABLED(CONFIG_SMP))
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return -EINVAL;
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ret = arc_get_timer_clk(node);
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if (ret)
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return ret;
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
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write_aux_reg(ARC_REG_TIMER1_CNT, 0);
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write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
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sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq);
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return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
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}
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/********** Clock Event Device *********/
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static int arc_timer_irq;
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/*
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* Arm the timer to interrupt after @cycles
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* The distinction for oneshot/periodic is done in arc_event_timer_ack() below
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*/
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static void arc_timer_event_setup(unsigned int cycles)
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{
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write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
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write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
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write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
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}
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static int arc_clkevent_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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arc_timer_event_setup(delta);
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return 0;
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}
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static int arc_clkevent_set_periodic(struct clock_event_device *dev)
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{
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/*
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* At X Hz, 1 sec = 1000ms -> X cycles;
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* 10ms -> X / 100 cycles
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*/
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arc_timer_event_setup(arc_timer_freq / HZ);
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return 0;
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}
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static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
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.name = "ARC Timer0",
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.features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_PERIODIC,
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.rating = 300,
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.set_next_event = arc_clkevent_set_next_event,
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.set_state_periodic = arc_clkevent_set_periodic,
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};
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static irqreturn_t timer_irq_handler(int irq, void *dev_id)
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{
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/*
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* Note that generic IRQ core could have passed @evt for @dev_id if
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* irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
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*/
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struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
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int irq_reenable = clockevent_state_periodic(evt);
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/*
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* 1. ACK the interrupt
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* - For ARC700, any write to CTRL reg ACKs it, so just rewrite
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* Count when [N]ot [H]alted bit.
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* - For HS3x, it is a bit subtle. On taken count-down interrupt,
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* IP bit [3] is set, which needs to be cleared for ACK'ing.
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* The write below can only update the other two bits, hence
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* explicitly clears IP bit
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* 2. Re-arm interrupt if periodic by writing to IE bit [0]
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*/
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write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int arc_timer_starting_cpu(unsigned int cpu)
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{
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struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
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evt->cpumask = cpumask_of(smp_processor_id());
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clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
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enable_percpu_irq(arc_timer_irq, 0);
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return 0;
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}
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static int arc_timer_dying_cpu(unsigned int cpu)
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{
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disable_percpu_irq(arc_timer_irq);
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return 0;
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}
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/*
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* clockevent setup for boot CPU
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*/
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static int __init arc_clockevent_setup(struct device_node *node)
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{
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struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
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int ret;
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arc_timer_irq = irq_of_parse_and_map(node, 0);
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if (arc_timer_irq <= 0) {
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pr_err("clockevent: missing irq\n");
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return -EINVAL;
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}
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ret = arc_get_timer_clk(node);
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if (ret) {
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pr_err("clockevent: missing clk\n");
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return ret;
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}
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/* Needs apriori irq_set_percpu_devid() done in intc map function */
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ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
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"Timer0 (per-cpu-tick)", evt);
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if (ret) {
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pr_err("clockevent: unable to request irq\n");
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return ret;
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}
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ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
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"clockevents/arc/timer:starting",
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arc_timer_starting_cpu,
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arc_timer_dying_cpu);
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if (ret) {
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pr_err("Failed to setup hotplug state\n");
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return ret;
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}
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return 0;
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}
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static int __init arc_of_timer_init(struct device_node *np)
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{
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static int init_count = 0;
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int ret;
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if (!init_count) {
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init_count = 1;
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ret = arc_clockevent_setup(np);
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} else {
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ret = arc_cs_setup_timer1(np);
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}
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return ret;
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}
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TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
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