634 строки
19 KiB
C
634 строки
19 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995 Waldorf GmbH
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* Copyright (C) 1994 - 2000, 06 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
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* Author: Maciej W. Rozycki <macro@mips.com>
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*/
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#ifndef _ASM_IO_H
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#define _ASM_IO_H
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/irqflags.h>
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#include <asm/addrspace.h>
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#include <asm/bug.h>
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#include <asm/byteorder.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm-generic/iomap.h>
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#include <asm/page.h>
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#include <asm/pgtable-bits.h>
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#include <asm/processor.h>
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#include <asm/string.h>
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#include <ioremap.h>
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#include <mangle-port.h>
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/*
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* Slowdown I/O port space accesses for antique hardware.
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*/
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#undef CONF_SLOWDOWN_IO
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/*
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* Raw operations are never swapped in software. OTOH values that raw
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* operations are working on may or may not have been swapped by the bus
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* hardware. An example use would be for flash memory that's used for
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* execute in place.
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*/
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# define __raw_ioswabb(a, x) (x)
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# define __raw_ioswabw(a, x) (x)
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# define __raw_ioswabl(a, x) (x)
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# define __raw_ioswabq(a, x) (x)
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# define ____raw_ioswabq(a, x) (x)
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/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
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#define IO_SPACE_LIMIT 0xffff
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/*
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* On MIPS I/O ports are memory mapped, so we access them using normal
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* load/store instructions. mips_io_port_base is the virtual address to
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* which all ports are being mapped. For sake of efficiency some code
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* assumes that this is an address that can be loaded with a single lui
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* instruction, so the lower 16 bits must be zero. Should be true on
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* on any sane architecture; generic code does not use this assumption.
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*/
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extern const unsigned long mips_io_port_base;
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/*
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* Gcc will generate code to load the value of mips_io_port_base after each
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* function call which may be fairly wasteful in some cases. So we don't
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* play quite by the book. We tell gcc mips_io_port_base is a long variable
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* which solves the code generation issue. Now we need to violate the
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* aliasing rules a little to make initialization possible and finally we
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* will need the barrier() to fight side effects of the aliasing chat.
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* This trickery will eventually collapse under gcc's optimizer. Oh well.
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*/
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static inline void set_io_port_base(unsigned long base)
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{
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* (unsigned long *) &mips_io_port_base = base;
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barrier();
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}
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/*
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* Thanks to James van Artsdalen for a better timing-fix than
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* the two short jumps: using outb's to a nonexistent port seems
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* to guarantee better timings even on fast machines.
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*
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* On the other hand, I'd like to be sure of a non-existent port:
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* I feel a bit unsafe about using 0x80 (should be safe, though)
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*
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* Linus
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*
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*/
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#define __SLOW_DOWN_IO \
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__asm__ __volatile__( \
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"sb\t$0,0x80(%0)" \
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: : "r" (mips_io_port_base));
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#ifdef CONF_SLOWDOWN_IO
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#ifdef REALLY_SLOW_IO
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#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
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#else
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#define SLOW_DOWN_IO __SLOW_DOWN_IO
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#endif
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#else
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#define SLOW_DOWN_IO
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#endif
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/*
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* virt_to_phys - map virtual addresses to physical
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* @address: address to remap
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*
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* The returned physical address is the physical (CPU) mapping for
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* the memory address given. It is only valid to use this function on
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* addresses directly mapped or allocated via kmalloc.
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*
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* This function does not give bus mappings for DMA transfers. In
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* almost all conceivable cases a device driver should not be using
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* this function
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*/
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static inline unsigned long virt_to_phys(volatile const void *address)
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{
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return __pa(address);
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}
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/*
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* phys_to_virt - map physical address to virtual
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* @address: address to remap
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*
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* The returned virtual address is a current CPU mapping for
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* the memory address given. It is only valid to use this function on
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* addresses that have a kernel mapping
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*
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* This function does not handle bus mappings for DMA transfers. In
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* almost all conceivable cases a device driver should not be using
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* this function
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*/
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static inline void * phys_to_virt(unsigned long address)
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{
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return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
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}
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/*
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* ISA I/O bus memory addresses are 1:1 with the physical address.
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*/
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static inline unsigned long isa_virt_to_bus(volatile void * address)
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{
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return (unsigned long)address - PAGE_OFFSET;
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}
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static inline void * isa_bus_to_virt(unsigned long address)
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{
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return (void *)(address + PAGE_OFFSET);
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}
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#define isa_page_to_bus page_to_phys
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/*
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* However PCI ones are not necessarily 1:1 and therefore these interfaces
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* are forbidden in portable PCI drivers.
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*
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* Allow them for x86 for legacy drivers, though.
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*/
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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/*
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* Change "struct page" to physical address.
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*/
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#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
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extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
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extern void __iounmap(const volatile void __iomem *addr);
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#ifndef CONFIG_PCI
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struct pci_dev;
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static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
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#endif
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static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
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unsigned long flags)
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{
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void __iomem *addr = plat_ioremap(offset, size, flags);
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if (addr)
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return addr;
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#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
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if (cpu_has_64bit_addresses) {
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u64 base = UNCAC_BASE;
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/*
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* R10000 supports a 2 bit uncached attribute therefore
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* UNCAC_BASE may not equal IO_BASE.
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*/
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if (flags == _CACHE_UNCACHED)
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base = (u64) IO_BASE;
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return (void __iomem *) (unsigned long) (base + offset);
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} else if (__builtin_constant_p(offset) &&
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__builtin_constant_p(size) && __builtin_constant_p(flags)) {
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phys_t phys_addr, last_addr;
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phys_addr = fixup_bigphys_addr(offset, size);
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/* Don't allow wraparound or zero size. */
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last_addr = phys_addr + size - 1;
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if (!size || last_addr < phys_addr)
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return NULL;
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/*
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* Map uncached objects in the low 512MB of address
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* space using KSEG1.
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*/
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if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
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flags == _CACHE_UNCACHED)
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return (void __iomem *)
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(unsigned long)CKSEG1ADDR(phys_addr);
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}
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return __ioremap(offset, size, flags);
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#undef __IS_LOW512
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}
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/*
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* ioremap - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*/
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#define ioremap(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_UNCACHED)
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/*
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* ioremap_nocache - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_nocache performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked uncachable
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* on the CPU as well as honouring existing caching rules from things like
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* the PCI bus. Note that there are other caches and buffers on many
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* busses. In particular driver authors should read up on PCI writes
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*
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* It's useful if some control registers are in such an area and
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* write combining or read caching is not desirable:
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*/
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#define ioremap_nocache(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_UNCACHED)
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/*
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* ioremap_cachable - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_nocache performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked cachable by
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* the CPU. Also enables full write-combining. Useful for some
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* memory-like regions on I/O busses.
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*/
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#define ioremap_cachable(offset, size) \
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__ioremap_mode((offset), (size), _page_cachable_default)
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/*
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* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
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* requests a cachable mapping, ioremap_uncached_accelerated requests a
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* mapping using the uncached accelerated mode which isn't supported on
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* all processors.
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*/
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#define ioremap_cacheable_cow(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
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#define ioremap_uncached_accelerated(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
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static inline void iounmap(const volatile void __iomem *addr)
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{
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if (plat_iounmap(addr))
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return;
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#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
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if (cpu_has_64bit_addresses ||
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(__builtin_constant_p(addr) && __IS_KSEG1(addr)))
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return;
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__iounmap(addr);
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#undef __IS_KSEG1
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}
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define war_octeon_io_reorder_wmb() wmb()
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#else
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#define war_octeon_io_reorder_wmb() do { } while (0)
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#endif
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#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
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\
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static inline void pfx##write##bwlq(type val, \
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volatile void __iomem *mem) \
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{ \
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volatile type *__mem; \
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type __val; \
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\
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war_octeon_io_reorder_wmb(); \
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\
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__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
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\
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__val = pfx##ioswab##bwlq(__mem, val); \
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\
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if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
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*__mem = __val; \
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else if (cpu_has_64bits) { \
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unsigned long __flags; \
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type __tmp; \
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\
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if (irq) \
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local_irq_save(__flags); \
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__asm__ __volatile__( \
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".set arch=r4000" "\t\t# __writeq""\n\t" \
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"dsll32 %L0, %L0, 0" "\n\t" \
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"dsrl32 %L0, %L0, 0" "\n\t" \
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"dsll32 %M0, %M0, 0" "\n\t" \
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"or %L0, %L0, %M0" "\n\t" \
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"sd %L0, %2" "\n\t" \
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".set mips0" "\n" \
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: "=r" (__tmp) \
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: "0" (__val), "m" (*__mem)); \
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if (irq) \
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local_irq_restore(__flags); \
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} else \
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BUG(); \
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} \
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\
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static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
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{ \
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volatile type *__mem; \
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type __val; \
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\
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__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
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\
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if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
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__val = *__mem; \
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else if (cpu_has_64bits) { \
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unsigned long __flags; \
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\
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if (irq) \
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local_irq_save(__flags); \
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__asm__ __volatile__( \
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".set arch=r4000" "\t\t# __readq" "\n\t" \
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"ld %L0, %1" "\n\t" \
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"dsra32 %M0, %L0, 0" "\n\t" \
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"sll %L0, %L0, 0" "\n\t" \
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".set mips0" "\n" \
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: "=r" (__val) \
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: "m" (*__mem)); \
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if (irq) \
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local_irq_restore(__flags); \
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} else { \
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__val = 0; \
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BUG(); \
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} \
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\
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return pfx##ioswab##bwlq(__mem, __val); \
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}
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#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
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\
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static inline void pfx##out##bwlq##p(type val, unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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war_octeon_io_reorder_wmb(); \
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\
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__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
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\
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__val = pfx##ioswab##bwlq(__addr, val); \
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\
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/* Really, we want this to be atomic */ \
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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*__addr = __val; \
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slow; \
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} \
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\
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static inline type pfx##in##bwlq##p(unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
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\
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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__val = *__addr; \
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slow; \
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\
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return pfx##ioswab##bwlq(__addr, __val); \
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}
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#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
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\
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__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
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#define BUILDIO_MEM(bwlq, type) \
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\
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__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
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__BUILD_MEMORY_PFX(, bwlq, type) \
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__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
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BUILDIO_MEM(b, u8)
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BUILDIO_MEM(w, u16)
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BUILDIO_MEM(l, u32)
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BUILDIO_MEM(q, u64)
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#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
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#define BUILDIO_IOPORT(bwlq, type) \
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__BUILD_IOPORT_PFX(, bwlq, type) \
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__BUILD_IOPORT_PFX(__mem_, bwlq, type)
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BUILDIO_IOPORT(b, u8)
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BUILDIO_IOPORT(w, u16)
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BUILDIO_IOPORT(l, u32)
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#ifdef CONFIG_64BIT
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BUILDIO_IOPORT(q, u64)
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#endif
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#define __BUILDIO(bwlq, type) \
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\
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__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
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__BUILDIO(q, u64)
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#define readb_relaxed readb
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#define readw_relaxed readw
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#define readl_relaxed readl
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#define readq_relaxed readq
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#define writeb_relaxed writeb
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#define writew_relaxed writew
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#define writel_relaxed writel
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#define writeq_relaxed writeq
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#define readb_be(addr) \
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__raw_readb((__force unsigned *)(addr))
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#define readw_be(addr) \
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be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
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#define readl_be(addr) \
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be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
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#define readq_be(addr) \
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be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
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#define writeb_be(val, addr) \
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__raw_writeb((val), (__force unsigned *)(addr))
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#define writew_be(val, addr) \
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__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
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#define writel_be(val, addr) \
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__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
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#define writeq_be(val, addr) \
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__raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
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/*
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* Some code tests for these symbols
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*/
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#define readq readq
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#define writeq writeq
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#define __BUILD_MEMORY_STRING(bwlq, type) \
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\
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static inline void writes##bwlq(volatile void __iomem *mem, \
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const void *addr, unsigned int count) \
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|
{ \
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const volatile type *__addr = addr; \
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\
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while (count--) { \
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__mem_write##bwlq(*__addr, mem); \
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__addr++; \
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} \
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} \
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\
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static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
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|
unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = __mem_read##bwlq(mem); \
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__addr++; \
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} \
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}
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|
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#define __BUILD_IOPORT_STRING(bwlq, type) \
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|
\
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|
static inline void outs##bwlq(unsigned long port, const void *addr, \
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|
unsigned int count) \
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|
{ \
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const volatile type *__addr = addr; \
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\
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while (count--) { \
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__mem_out##bwlq(*__addr, port); \
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__addr++; \
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} \
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} \
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\
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static inline void ins##bwlq(unsigned long port, void *addr, \
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|
unsigned int count) \
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|
{ \
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volatile type *__addr = addr; \
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|
\
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while (count--) { \
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*__addr = __mem_in##bwlq(port); \
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__addr++; \
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} \
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}
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|
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#define BUILDSTRING(bwlq, type) \
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|
\
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__BUILD_MEMORY_STRING(bwlq, type) \
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__BUILD_IOPORT_STRING(bwlq, type)
|
|
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|
BUILDSTRING(b, u8)
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|
BUILDSTRING(w, u16)
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|
BUILDSTRING(l, u32)
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|
#ifdef CONFIG_64BIT
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|
BUILDSTRING(q, u64)
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#endif
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|
|
|
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|
#ifdef CONFIG_CPU_CAVIUM_OCTEON
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|
#define mmiowb() wmb()
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|
#else
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|
/* Depends on MIPS II instruction set */
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|
#define mmiowb() asm volatile ("sync" ::: "memory")
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|
#endif
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|
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|
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
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|
{
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|
memset((void __force *) addr, val, count);
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|
}
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|
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
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|
{
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|
memcpy(dst, (void __force *) src, count);
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|
}
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|
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
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|
{
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|
memcpy((void __force *) dst, src, count);
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|
}
|
|
|
|
/*
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|
* The caches on some architectures aren't dma-coherent and have need to
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|
* handle this in software. There are three types of operations that
|
|
* can be applied to dma buffers.
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|
*
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|
* - dma_cache_wback_inv(start, size) makes caches and coherent by
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|
* writing the content of the caches back to memory, if necessary.
|
|
* The function also invalidates the affected part of the caches as
|
|
* necessary before DMA transfers from outside to memory.
|
|
* - dma_cache_wback(start, size) makes caches and coherent by
|
|
* writing the content of the caches back to memory, if necessary.
|
|
* The function also invalidates the affected part of the caches as
|
|
* necessary before DMA transfers from outside to memory.
|
|
* - dma_cache_inv(start, size) invalidates the affected parts of the
|
|
* caches. Dirty lines of the caches may be written back or simply
|
|
* be discarded. This operation is necessary before dma operations
|
|
* to the memory.
|
|
*
|
|
* This API used to be exported; it now is for arch code internal use only.
|
|
*/
|
|
#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
|
|
|
|
extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
|
|
extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
|
|
extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
|
|
|
|
#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
|
|
#define dma_cache_wback(start, size) _dma_cache_wback(start, size)
|
|
#define dma_cache_inv(start, size) _dma_cache_inv(start, size)
|
|
|
|
#else /* Sane hardware */
|
|
|
|
#define dma_cache_wback_inv(start,size) \
|
|
do { (void) (start); (void) (size); } while (0)
|
|
#define dma_cache_wback(start,size) \
|
|
do { (void) (start); (void) (size); } while (0)
|
|
#define dma_cache_inv(start,size) \
|
|
do { (void) (start); (void) (size); } while (0)
|
|
|
|
#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
|
|
|
|
/*
|
|
* Read a 32-bit register that requires a 64-bit read cycle on the bus.
|
|
* Avoid interrupt mucking, just adjust the address for 4-byte access.
|
|
* Assume the addresses are 8-byte aligned.
|
|
*/
|
|
#ifdef __MIPSEB__
|
|
#define __CSR_32_ADJUST 4
|
|
#else
|
|
#define __CSR_32_ADJUST 0
|
|
#endif
|
|
|
|
#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
|
|
#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
|
|
|
|
/*
|
|
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
|
* access
|
|
*/
|
|
#define xlate_dev_mem_ptr(p) __va(p)
|
|
|
|
/*
|
|
* Convert a virtual cached pointer to an uncached pointer
|
|
*/
|
|
#define xlate_dev_kmem_ptr(p) p
|
|
|
|
#endif /* _ASM_IO_H */
|