704 строки
16 KiB
C
704 строки
16 KiB
C
/*
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* Copyright (c) 1996-2004 Russell King.
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*
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* Please note that this platform does not support 32-bit IDE IO.
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*/
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#include <linux/string.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/blkdev.h>
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#include <linux/errno.h>
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#include <linux/ide.h>
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#include <linux/dma-mapping.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/scatterlist.h>
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#include <linux/io.h>
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#include <asm/dma.h>
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#include <asm/ecard.h>
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#define DRV_NAME "icside"
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#define ICS_IDENT_OFFSET 0x2280
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#define ICS_ARCIN_V5_INTRSTAT 0x0000
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#define ICS_ARCIN_V5_INTROFFSET 0x0004
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#define ICS_ARCIN_V5_IDEOFFSET 0x2800
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#define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
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#define ICS_ARCIN_V5_IDESTEPPING 6
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#define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
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#define ICS_ARCIN_V6_INTROFFSET_1 0x2200
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#define ICS_ARCIN_V6_INTRSTAT_1 0x2290
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#define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
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#define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
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#define ICS_ARCIN_V6_INTROFFSET_2 0x3200
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#define ICS_ARCIN_V6_INTRSTAT_2 0x3290
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#define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
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#define ICS_ARCIN_V6_IDESTEPPING 6
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struct cardinfo {
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unsigned int dataoffset;
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unsigned int ctrloffset;
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unsigned int stepping;
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};
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static struct cardinfo icside_cardinfo_v5 = {
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.dataoffset = ICS_ARCIN_V5_IDEOFFSET,
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.ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET,
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.stepping = ICS_ARCIN_V5_IDESTEPPING,
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};
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static struct cardinfo icside_cardinfo_v6_1 = {
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.dataoffset = ICS_ARCIN_V6_IDEOFFSET_1,
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.ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1,
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.stepping = ICS_ARCIN_V6_IDESTEPPING,
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};
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static struct cardinfo icside_cardinfo_v6_2 = {
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.dataoffset = ICS_ARCIN_V6_IDEOFFSET_2,
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.ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2,
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.stepping = ICS_ARCIN_V6_IDESTEPPING,
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};
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struct icside_state {
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unsigned int channel;
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unsigned int enabled;
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void __iomem *irq_port;
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void __iomem *ioc_base;
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unsigned int sel;
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unsigned int type;
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struct ide_host *host;
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};
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#define ICS_TYPE_A3IN 0
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#define ICS_TYPE_A3USER 1
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#define ICS_TYPE_V6 3
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#define ICS_TYPE_V5 15
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#define ICS_TYPE_NOTYPE ((unsigned int)-1)
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/* ---------------- Version 5 PCB Support Functions --------------------- */
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/* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
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* Purpose : enable interrupts from card
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*/
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static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
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{
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struct icside_state *state = ec->irq_data;
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writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
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}
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/* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
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* Purpose : disable interrupts from card
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*/
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static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
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{
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struct icside_state *state = ec->irq_data;
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readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
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}
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static const expansioncard_ops_t icside_ops_arcin_v5 = {
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.irqenable = icside_irqenable_arcin_v5,
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.irqdisable = icside_irqdisable_arcin_v5,
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};
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/* ---------------- Version 6 PCB Support Functions --------------------- */
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/* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
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* Purpose : enable interrupts from card
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*/
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static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
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{
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struct icside_state *state = ec->irq_data;
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void __iomem *base = state->irq_port;
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state->enabled = 1;
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switch (state->channel) {
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case 0:
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writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
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readb(base + ICS_ARCIN_V6_INTROFFSET_2);
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break;
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case 1:
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writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
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readb(base + ICS_ARCIN_V6_INTROFFSET_1);
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break;
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}
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}
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/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
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* Purpose : disable interrupts from card
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*/
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static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
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{
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struct icside_state *state = ec->irq_data;
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state->enabled = 0;
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readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
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readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
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}
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/* Prototype: icside_irqprobe(struct expansion_card *ec)
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* Purpose : detect an active interrupt from card
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*/
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static int icside_irqpending_arcin_v6(struct expansion_card *ec)
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{
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struct icside_state *state = ec->irq_data;
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return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
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readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
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}
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static const expansioncard_ops_t icside_ops_arcin_v6 = {
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.irqenable = icside_irqenable_arcin_v6,
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.irqdisable = icside_irqdisable_arcin_v6,
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.irqpending = icside_irqpending_arcin_v6,
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};
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/*
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* Handle routing of interrupts. This is called before
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* we write the command to the drive.
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*/
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static void icside_maskproc(ide_drive_t *drive, int mask)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct expansion_card *ec = ECARD_DEV(hwif->dev);
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struct icside_state *state = ecard_get_drvdata(ec);
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unsigned long flags;
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local_irq_save(flags);
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state->channel = hwif->channel;
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if (state->enabled && !mask) {
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switch (hwif->channel) {
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case 0:
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writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
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readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
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break;
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case 1:
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writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
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readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
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break;
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}
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} else {
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readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
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readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
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}
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local_irq_restore(flags);
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}
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static const struct ide_port_ops icside_v6_no_dma_port_ops = {
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.maskproc = icside_maskproc,
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};
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#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
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/*
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* SG-DMA support.
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*
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* Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
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* There is only one DMA controller per card, which means that only
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* one drive can be accessed at one time. NOTE! We do not enforce that
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* here, but we rely on the main IDE driver spotting that both
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* interfaces use the same IRQ, which should guarantee this.
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*/
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/*
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* Configure the IOMD to give the appropriate timings for the transfer
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* mode being requested. We take the advice of the ATA standards, and
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* calculate the cycle time based on the transfer mode, and the EIDE
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* MW DMA specs that the drive provides in the IDENTIFY command.
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*
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* We have the following IOMD DMA modes to choose from:
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*
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* Type Active Recovery Cycle
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* A 250 (250) 312 (550) 562 (800)
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* B 187 250 437
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* C 125 (125) 125 (375) 250 (500)
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* D 62 125 187
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*
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* (figures in brackets are actual measured timings)
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*
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* However, we also need to take care of the read/write active and
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* recovery timings:
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*
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* Read Write
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* Mode Active -- Recovery -- Cycle IOMD type
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* MW0 215 50 215 480 A
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* MW1 80 50 50 150 C
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* MW2 70 25 25 120 C
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*/
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static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
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{
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int cycle_time, use_dma_info = 0;
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switch (xfer_mode) {
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case XFER_MW_DMA_2:
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cycle_time = 250;
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use_dma_info = 1;
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break;
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case XFER_MW_DMA_1:
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cycle_time = 250;
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use_dma_info = 1;
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break;
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case XFER_MW_DMA_0:
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cycle_time = 480;
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break;
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case XFER_SW_DMA_2:
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case XFER_SW_DMA_1:
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case XFER_SW_DMA_0:
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cycle_time = 480;
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break;
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}
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/*
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* If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
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* take care to note the values in the ID...
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*/
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if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time)
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cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME];
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drive->drive_data = cycle_time;
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printk("%s: %s selected (peak %dMB/s)\n", drive->name,
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ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
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}
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static const struct ide_port_ops icside_v6_port_ops = {
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.set_dma_mode = icside_set_dma_mode,
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.maskproc = icside_maskproc,
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};
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static void icside_dma_host_set(ide_drive_t *drive, int on)
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{
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}
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static int icside_dma_end(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct expansion_card *ec = ECARD_DEV(hwif->dev);
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drive->waiting_for_dma = 0;
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disable_dma(ec->dma);
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/* Teardown mappings after DMA has completed. */
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ide_destroy_dmatable(drive);
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return get_dma_residue(ec->dma) != 0;
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}
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static void icside_dma_start(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct expansion_card *ec = ECARD_DEV(hwif->dev);
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/* We can not enable DMA on both channels simultaneously. */
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BUG_ON(dma_channel_active(ec->dma));
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enable_dma(ec->dma);
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}
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static int icside_dma_setup(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct expansion_card *ec = ECARD_DEV(hwif->dev);
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struct icside_state *state = ecard_get_drvdata(ec);
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struct request *rq = hwif->hwgroup->rq;
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unsigned int dma_mode;
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if (rq_data_dir(rq))
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dma_mode = DMA_MODE_WRITE;
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else
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dma_mode = DMA_MODE_READ;
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/*
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* We can not enable DMA on both channels.
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*/
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BUG_ON(dma_channel_active(ec->dma));
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hwif->sg_nents = ide_build_sglist(drive, rq);
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/*
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* Ensure that we have the right interrupt routed.
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*/
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icside_maskproc(drive, 0);
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/*
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* Route the DMA signals to the correct interface.
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*/
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writeb(state->sel | hwif->channel, state->ioc_base);
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/*
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* Select the correct timing for this drive.
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*/
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set_dma_speed(ec->dma, drive->drive_data);
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/*
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* Tell the DMA engine about the SG table and
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* data direction.
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*/
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set_dma_sg(ec->dma, hwif->sg_table, hwif->sg_nents);
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set_dma_mode(ec->dma, dma_mode);
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drive->waiting_for_dma = 1;
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return 0;
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}
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static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
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{
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/* issue cmd to drive */
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ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
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}
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static int icside_dma_test_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct expansion_card *ec = ECARD_DEV(hwif->dev);
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struct icside_state *state = ecard_get_drvdata(ec);
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return readb(state->irq_port +
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(hwif->channel ?
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ICS_ARCIN_V6_INTRSTAT_2 :
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ICS_ARCIN_V6_INTRSTAT_1)) & 1;
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}
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static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
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{
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hwif->dmatable_cpu = NULL;
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hwif->dmatable_dma = 0;
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return 0;
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}
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static const struct ide_dma_ops icside_v6_dma_ops = {
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.dma_host_set = icside_dma_host_set,
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.dma_setup = icside_dma_setup,
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.dma_exec_cmd = icside_dma_exec_cmd,
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.dma_start = icside_dma_start,
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.dma_end = icside_dma_end,
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.dma_test_irq = icside_dma_test_irq,
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.dma_timeout = ide_dma_timeout,
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.dma_lost_irq = ide_dma_lost_irq,
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};
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#else
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#define icside_v6_dma_ops NULL
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#endif
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static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d)
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{
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return -EOPNOTSUPP;
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}
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static void icside_setup_ports(hw_regs_t *hw, void __iomem *base,
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struct cardinfo *info, struct expansion_card *ec)
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{
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unsigned long port = (unsigned long)base + info->dataoffset;
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hw->io_ports.data_addr = port;
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hw->io_ports.error_addr = port + (1 << info->stepping);
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hw->io_ports.nsect_addr = port + (2 << info->stepping);
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hw->io_ports.lbal_addr = port + (3 << info->stepping);
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hw->io_ports.lbam_addr = port + (4 << info->stepping);
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hw->io_ports.lbah_addr = port + (5 << info->stepping);
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hw->io_ports.device_addr = port + (6 << info->stepping);
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hw->io_ports.status_addr = port + (7 << info->stepping);
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hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset;
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hw->irq = ec->irq;
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hw->dev = &ec->dev;
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hw->chipset = ide_acorn;
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}
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static int __init
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icside_register_v5(struct icside_state *state, struct expansion_card *ec)
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{
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void __iomem *base;
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struct ide_host *host;
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hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
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int ret;
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base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
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if (!base)
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return -ENOMEM;
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state->irq_port = base;
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ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
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ec->irqmask = 1;
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ecard_setirq(ec, &icside_ops_arcin_v5, state);
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/*
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* Be on the safe side - disable interrupts
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*/
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icside_irqdisable_arcin_v5(ec, 0);
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icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);
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host = ide_host_alloc(NULL, hws);
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if (host == NULL)
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return -ENODEV;
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state->host = host;
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ecard_set_drvdata(ec, state);
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ret = ide_host_register(host, NULL, hws);
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if (ret)
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goto err_free;
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return 0;
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err_free:
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ide_host_free(host);
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ecard_set_drvdata(ec, NULL);
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return ret;
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}
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static const struct ide_port_info icside_v6_port_info __initdata = {
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.init_dma = icside_dma_off_init,
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.port_ops = &icside_v6_no_dma_port_ops,
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.dma_ops = &icside_v6_dma_ops,
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.host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
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.mwdma_mask = ATA_MWDMA2,
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.swdma_mask = ATA_SWDMA2,
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};
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static int __init
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icside_register_v6(struct icside_state *state, struct expansion_card *ec)
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{
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void __iomem *ioc_base, *easi_base;
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struct ide_host *host;
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unsigned int sel = 0;
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int ret;
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hw_regs_t hw[2], *hws[] = { &hw[0], NULL, NULL, NULL };
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struct ide_port_info d = icside_v6_port_info;
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ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
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if (!ioc_base) {
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ret = -ENOMEM;
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goto out;
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}
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easi_base = ioc_base;
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|
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if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
|
|
easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
|
|
if (!easi_base) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Enable access to the EASI region.
|
|
*/
|
|
sel = 1 << 5;
|
|
}
|
|
|
|
writeb(sel, ioc_base);
|
|
|
|
ecard_setirq(ec, &icside_ops_arcin_v6, state);
|
|
|
|
state->irq_port = easi_base;
|
|
state->ioc_base = ioc_base;
|
|
state->sel = sel;
|
|
|
|
/*
|
|
* Be on the safe side - disable interrupts
|
|
*/
|
|
icside_irqdisable_arcin_v6(ec, 0);
|
|
|
|
icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
|
|
icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);
|
|
|
|
host = ide_host_alloc(&d, hws);
|
|
if (host == NULL)
|
|
return -ENODEV;
|
|
|
|
state->host = host;
|
|
|
|
ecard_set_drvdata(ec, state);
|
|
|
|
if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
|
|
d.init_dma = icside_dma_init;
|
|
d.port_ops = &icside_v6_port_ops;
|
|
d.dma_ops = NULL;
|
|
}
|
|
|
|
ret = ide_host_register(host, NULL, hws);
|
|
if (ret)
|
|
goto err_free;
|
|
|
|
return 0;
|
|
err_free:
|
|
ide_host_free(host);
|
|
if (d.dma_ops)
|
|
free_dma(ec->dma);
|
|
ecard_set_drvdata(ec, NULL);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int __devinit
|
|
icside_probe(struct expansion_card *ec, const struct ecard_id *id)
|
|
{
|
|
struct icside_state *state;
|
|
void __iomem *idmem;
|
|
int ret;
|
|
|
|
ret = ecard_request_resources(ec);
|
|
if (ret)
|
|
goto out;
|
|
|
|
state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
|
|
if (!state) {
|
|
ret = -ENOMEM;
|
|
goto release;
|
|
}
|
|
|
|
state->type = ICS_TYPE_NOTYPE;
|
|
|
|
idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
|
|
if (idmem) {
|
|
unsigned int type;
|
|
|
|
type = readb(idmem + ICS_IDENT_OFFSET) & 1;
|
|
type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
|
|
type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
|
|
type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
|
|
ecardm_iounmap(ec, idmem);
|
|
|
|
state->type = type;
|
|
}
|
|
|
|
switch (state->type) {
|
|
case ICS_TYPE_A3IN:
|
|
dev_warn(&ec->dev, "A3IN unsupported\n");
|
|
ret = -ENODEV;
|
|
break;
|
|
|
|
case ICS_TYPE_A3USER:
|
|
dev_warn(&ec->dev, "A3USER unsupported\n");
|
|
ret = -ENODEV;
|
|
break;
|
|
|
|
case ICS_TYPE_V5:
|
|
ret = icside_register_v5(state, ec);
|
|
break;
|
|
|
|
case ICS_TYPE_V6:
|
|
ret = icside_register_v6(state, ec);
|
|
break;
|
|
|
|
default:
|
|
dev_warn(&ec->dev, "unknown interface type\n");
|
|
ret = -ENODEV;
|
|
break;
|
|
}
|
|
|
|
if (ret == 0)
|
|
goto out;
|
|
|
|
kfree(state);
|
|
release:
|
|
ecard_release_resources(ec);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static void __devexit icside_remove(struct expansion_card *ec)
|
|
{
|
|
struct icside_state *state = ecard_get_drvdata(ec);
|
|
|
|
switch (state->type) {
|
|
case ICS_TYPE_V5:
|
|
/* FIXME: tell IDE to stop using the interface */
|
|
|
|
/* Disable interrupts */
|
|
icside_irqdisable_arcin_v5(ec, 0);
|
|
break;
|
|
|
|
case ICS_TYPE_V6:
|
|
/* FIXME: tell IDE to stop using the interface */
|
|
if (ec->dma != NO_DMA)
|
|
free_dma(ec->dma);
|
|
|
|
/* Disable interrupts */
|
|
icside_irqdisable_arcin_v6(ec, 0);
|
|
|
|
/* Reset the ROM pointer/EASI selection */
|
|
writeb(0, state->ioc_base);
|
|
break;
|
|
}
|
|
|
|
ecard_set_drvdata(ec, NULL);
|
|
|
|
kfree(state);
|
|
ecard_release_resources(ec);
|
|
}
|
|
|
|
static void icside_shutdown(struct expansion_card *ec)
|
|
{
|
|
struct icside_state *state = ecard_get_drvdata(ec);
|
|
unsigned long flags;
|
|
|
|
/*
|
|
* Disable interrupts from this card. We need to do
|
|
* this before disabling EASI since we may be accessing
|
|
* this register via that region.
|
|
*/
|
|
local_irq_save(flags);
|
|
ec->ops->irqdisable(ec, 0);
|
|
local_irq_restore(flags);
|
|
|
|
/*
|
|
* Reset the ROM pointer so that we can read the ROM
|
|
* after a soft reboot. This also disables access to
|
|
* the IDE taskfile via the EASI region.
|
|
*/
|
|
if (state->ioc_base)
|
|
writeb(0, state->ioc_base);
|
|
}
|
|
|
|
static const struct ecard_id icside_ids[] = {
|
|
{ MANU_ICS, PROD_ICS_IDE },
|
|
{ MANU_ICS2, PROD_ICS2_IDE },
|
|
{ 0xffff, 0xffff }
|
|
};
|
|
|
|
static struct ecard_driver icside_driver = {
|
|
.probe = icside_probe,
|
|
.remove = __devexit_p(icside_remove),
|
|
.shutdown = icside_shutdown,
|
|
.id_table = icside_ids,
|
|
.drv = {
|
|
.name = "icside",
|
|
},
|
|
};
|
|
|
|
static int __init icside_init(void)
|
|
{
|
|
return ecard_register_driver(&icside_driver);
|
|
}
|
|
|
|
static void __exit icside_exit(void)
|
|
{
|
|
ecard_remove_driver(&icside_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("ICS IDE driver");
|
|
|
|
module_init(icside_init);
|
|
module_exit(icside_exit);
|