Dave Jiang d5081bf5dc ntb: intel: fix port config status offset for SPR ... The field offset for port configuration status on SPR has been changed to bit 14 from ICX where it resides at bit 12. By chance link status detection continued to work on SPR. This is due to bit 12 being a configuration bit which is in sync with the status bit. Fix this by checking for a SPR device and checking correct status bit. Fixes: 26bfe3d0b2 ("ntb: intel: Add Icelake (gen4) support for Intel NTB") Tested-by: Jerry Dai <jerry.dai@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>		2022-01-28 10:19:16 -05:00
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Kconfig	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
Makefile	ntb: intel: Add Icelake (gen4) support for Intel NTB	2020-04-20 10:16:23 -04:00
ntb_hw_gen1.c	NTB: switch from 'pci_' to 'dma_' API	2021-09-05 18:08:14 -04:00
ntb_hw_gen1.h	ntb: intel: add Intel NTB LTR vendor support for gen4 NTB	2020-12-06 18:18:03 -05:00
ntb_hw_gen3.c	ntb: intel: Add Icelake (gen4) support for Intel NTB	2020-04-20 10:16:23 -04:00
ntb_hw_gen3.h	ntb: intel: constify ioreadX() iomem argument (as in generic implementation)	2020-08-14 19:56:57 -07:00
ntb_hw_gen4.c	ntb: intel: fix port config status offset for SPR	2022-01-28 10:19:16 -05:00
ntb_hw_gen4.h	ntb: intel: fix port config status offset for SPR	2022-01-28 10:19:16 -05:00
ntb_hw_intel.h	ntb: intel: remove invalid email address in header comment	2021-09-04 18:36:04 -04:00