679 строки
31 KiB
C
679 строки
31 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* provides masks and opcode images for use by code generation, emulation
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* and for instructions that older assemblers might not know about
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*/
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#ifndef _ASM_POWERPC_PPC_OPCODE_H
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#define _ASM_POWERPC_PPC_OPCODE_H
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#include <asm/asm-const.h>
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#define __REG_R0 0
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#define __REG_R1 1
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#define __REG_R2 2
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#define __REG_R3 3
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#define __REG_R4 4
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#define __REG_R5 5
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#define __REG_R6 6
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#define __REG_R7 7
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#define __REG_R8 8
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#define __REG_R9 9
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#define __REG_R10 10
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#define __REG_R11 11
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#define __REG_R12 12
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#define __REG_R13 13
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#define __REG_R14 14
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#define __REG_R15 15
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#define __REG_R16 16
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#define __REG_R17 17
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#define __REG_R18 18
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#define __REG_R19 19
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#define __REG_R20 20
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#define __REG_R21 21
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#define __REG_R22 22
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#define __REG_R23 23
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#define __REG_R24 24
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#define __REG_R25 25
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#define __REG_R26 26
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#define __REG_R27 27
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#define __REG_R28 28
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#define __REG_R29 29
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#define __REG_R30 30
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#define __REG_R31 31
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#define __REGA0_0 0
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#define __REGA0_R1 1
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#define __REGA0_R2 2
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#define __REGA0_R3 3
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#define __REGA0_R4 4
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#define __REGA0_R5 5
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#define __REGA0_R6 6
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#define __REGA0_R7 7
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#define __REGA0_R8 8
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#define __REGA0_R9 9
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#define __REGA0_R10 10
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#define __REGA0_R11 11
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#define __REGA0_R12 12
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#define __REGA0_R13 13
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#define __REGA0_R14 14
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#define __REGA0_R15 15
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#define __REGA0_R16 16
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#define __REGA0_R17 17
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#define __REGA0_R18 18
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#define __REGA0_R19 19
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#define __REGA0_R20 20
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#define __REGA0_R21 21
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#define __REGA0_R22 22
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#define __REGA0_R23 23
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#define __REGA0_R24 24
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#define __REGA0_R25 25
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#define __REGA0_R26 26
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#define __REGA0_R27 27
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#define __REGA0_R28 28
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#define __REGA0_R29 29
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#define __REGA0_R30 30
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#define __REGA0_R31 31
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/* For use with PPC_RAW_() macros */
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#define _R0 0
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#define _R1 1
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#define _R2 2
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#define _R3 3
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#define _R4 4
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#define _R5 5
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#define _R6 6
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#define _R7 7
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#define _R8 8
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#define _R9 9
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#define _R10 10
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#define _R11 11
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#define _R12 12
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#define _R13 13
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#define _R14 14
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#define _R15 15
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#define _R16 16
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#define _R17 17
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#define _R18 18
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#define _R19 19
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#define _R20 20
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#define _R21 21
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#define _R22 22
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#define _R23 23
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#define _R24 24
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#define _R25 25
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#define _R26 26
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#define _R27 27
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#define _R28 28
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#define _R29 29
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#define _R30 30
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#define _R31 31
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#define IMM_L(i) ((uintptr_t)(i) & 0xffff)
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#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
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#define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0)
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#define IMM_D0(i) (((uintptr_t)(i) >> 16) & 0x3ffff)
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#define IMM_D1(i) IMM_L(i)
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/*
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* 16-bit immediate helper macros: HA() is for use with sign-extending instrs
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* (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the
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* top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
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*/
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#define IMM_H(i) ((uintptr_t)(i)>>16)
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#define IMM_HA(i) (((uintptr_t)(i)>>16) + \
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(((uintptr_t)(i) & 0x8000) >> 15))
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/* opcode and xopcode for instructions */
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#define OP_TRAP 3
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#define OP_TRAP_64 2
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#define OP_31_XOP_TRAP 4
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#define OP_31_XOP_LDX 21
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#define OP_31_XOP_LWZX 23
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#define OP_31_XOP_LDUX 53
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#define OP_31_XOP_DCBST 54
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#define OP_31_XOP_LWZUX 55
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#define OP_31_XOP_TRAP_64 68
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#define OP_31_XOP_DCBF 86
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#define OP_31_XOP_LBZX 87
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#define OP_31_XOP_STDX 149
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#define OP_31_XOP_STWX 151
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#define OP_31_XOP_STDUX 181
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#define OP_31_XOP_STWUX 183
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#define OP_31_XOP_STBX 215
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#define OP_31_XOP_LBZUX 119
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#define OP_31_XOP_STBUX 247
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#define OP_31_XOP_LHZX 279
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#define OP_31_XOP_LHZUX 311
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#define OP_31_XOP_MSGSNDP 142
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#define OP_31_XOP_MSGCLRP 174
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#define OP_31_XOP_TLBIE 306
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#define OP_31_XOP_MFSPR 339
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#define OP_31_XOP_LWAX 341
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#define OP_31_XOP_LHAX 343
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#define OP_31_XOP_LWAUX 373
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#define OP_31_XOP_LHAUX 375
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#define OP_31_XOP_STHX 407
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#define OP_31_XOP_STHUX 439
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#define OP_31_XOP_MTSPR 467
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#define OP_31_XOP_DCBI 470
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#define OP_31_XOP_LDBRX 532
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#define OP_31_XOP_LWBRX 534
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#define OP_31_XOP_TLBSYNC 566
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#define OP_31_XOP_STDBRX 660
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#define OP_31_XOP_STWBRX 662
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#define OP_31_XOP_STFSX 663
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#define OP_31_XOP_STFSUX 695
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#define OP_31_XOP_STFDX 727
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#define OP_31_XOP_STFDUX 759
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#define OP_31_XOP_LHBRX 790
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#define OP_31_XOP_LFIWAX 855
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#define OP_31_XOP_LFIWZX 887
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#define OP_31_XOP_STHBRX 918
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#define OP_31_XOP_STFIWX 983
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/* VSX Scalar Load Instructions */
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#define OP_31_XOP_LXSDX 588
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#define OP_31_XOP_LXSSPX 524
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#define OP_31_XOP_LXSIWAX 76
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#define OP_31_XOP_LXSIWZX 12
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/* VSX Scalar Store Instructions */
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#define OP_31_XOP_STXSDX 716
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#define OP_31_XOP_STXSSPX 652
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#define OP_31_XOP_STXSIWX 140
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/* VSX Vector Load Instructions */
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#define OP_31_XOP_LXVD2X 844
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#define OP_31_XOP_LXVW4X 780
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/* VSX Vector Load and Splat Instruction */
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#define OP_31_XOP_LXVDSX 332
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/* VSX Vector Store Instructions */
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#define OP_31_XOP_STXVD2X 972
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#define OP_31_XOP_STXVW4X 908
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#define OP_31_XOP_LFSX 535
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#define OP_31_XOP_LFSUX 567
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#define OP_31_XOP_LFDX 599
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#define OP_31_XOP_LFDUX 631
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/* VMX Vector Load Instructions */
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#define OP_31_XOP_LVX 103
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/* VMX Vector Store Instructions */
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#define OP_31_XOP_STVX 231
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/* Prefixed Instructions */
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#define OP_PREFIX 1
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#define OP_31 31
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#define OP_LWZ 32
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#define OP_STFS 52
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#define OP_STFSU 53
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#define OP_STFD 54
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#define OP_STFDU 55
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#define OP_LD 58
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#define OP_LWZU 33
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#define OP_LBZ 34
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#define OP_LBZU 35
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#define OP_STW 36
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#define OP_STWU 37
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#define OP_STD 62
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#define OP_STB 38
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#define OP_STBU 39
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#define OP_LHZ 40
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#define OP_LHZU 41
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#define OP_LHA 42
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#define OP_LHAU 43
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#define OP_STH 44
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#define OP_STHU 45
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#define OP_LMW 46
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#define OP_STMW 47
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#define OP_LFS 48
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#define OP_LFSU 49
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#define OP_LFD 50
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#define OP_LFDU 51
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#define OP_STFS 52
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#define OP_STFSU 53
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#define OP_STFD 54
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#define OP_STFDU 55
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#define OP_LQ 56
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/* sorted alphabetically */
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#define PPC_INST_BCCTR_FLUSH 0x4c400420
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#define PPC_INST_COPY 0x7c20060c
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#define PPC_INST_DCBA 0x7c0005ec
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#define PPC_INST_DCBA_MASK 0xfc0007fe
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#define PPC_INST_ISEL 0x7c00001e
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#define PPC_INST_ISEL_MASK 0xfc00003e
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#define PPC_INST_LSWI 0x7c0004aa
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#define PPC_INST_LSWX 0x7c00042a
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#define PPC_INST_LWSYNC 0x7c2004ac
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#define PPC_INST_SYNC 0x7c0004ac
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#define PPC_INST_SYNC_MASK 0xfc0007fe
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#define PPC_INST_MCRXR 0x7c000400
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#define PPC_INST_MCRXR_MASK 0xfc0007fe
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#define PPC_INST_MFSPR_PVR 0x7c1f42a6
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#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
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#define PPC_INST_MTMSRD 0x7c000164
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#define PPC_INST_POPCNTB 0x7c0000f4
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#define PPC_INST_POPCNTB_MASK 0xfc0007fe
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#define PPC_INST_RFEBB 0x4c000124
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#define PPC_INST_RFID 0x4c000024
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#define PPC_INST_MFSPR_DSCR 0x7c1102a6
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#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
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#define PPC_INST_MTSPR_DSCR 0x7c1103a6
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#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
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#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
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#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
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#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
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#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
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#define PPC_INST_STRING 0x7c00042a
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#define PPC_INST_STRING_MASK 0xfc0007fe
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#define PPC_INST_STRING_GEN_MASK 0xfc00067e
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#define PPC_INST_SETB 0x7c000100
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#define PPC_INST_STSWI 0x7c0005aa
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#define PPC_INST_STSWX 0x7c00052a
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#define PPC_INST_TRECHKPT 0x7c0007dd
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#define PPC_INST_TRECLAIM 0x7c00075d
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#define PPC_INST_TSR 0x7c0005dd
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#define PPC_INST_LD 0xe8000000
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#define PPC_INST_STD 0xf8000000
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#define PPC_INST_ADDIS 0x3c000000
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#define PPC_INST_ADD 0x7c000214
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#define PPC_INST_DIVD 0x7c0003d2
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#define PPC_INST_BRANCH 0x48000000
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#define PPC_INST_BL 0x48000001
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#define PPC_INST_BRANCH_COND 0x40800000
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/* Prefixes */
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#define PPC_INST_LFS 0xc0000000
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#define PPC_INST_STFS 0xd0000000
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#define PPC_INST_LFD 0xc8000000
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#define PPC_INST_STFD 0xd8000000
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#define PPC_PREFIX_MLS 0x06000000
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#define PPC_PREFIX_8LS 0x04000000
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/* Prefixed instructions */
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#define PPC_INST_PLD 0xe4000000
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#define PPC_INST_PSTD 0xf4000000
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/* macros to insert fields into opcodes */
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#define ___PPC_RA(a) (((a) & 0x1f) << 16)
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#define ___PPC_RB(b) (((b) & 0x1f) << 11)
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#define ___PPC_RC(c) (((c) & 0x1f) << 6)
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#define ___PPC_RS(s) (((s) & 0x1f) << 21)
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#define ___PPC_RT(t) ___PPC_RS(t)
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#define ___PPC_R(r) (((r) & 0x1) << 16)
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#define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
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#define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
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#define __PPC_RA(a) ___PPC_RA(__REG_##a)
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#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
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#define __PPC_RB(b) ___PPC_RB(__REG_##b)
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#define __PPC_RS(s) ___PPC_RS(__REG_##s)
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#define __PPC_RT(t) ___PPC_RT(__REG_##t)
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#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
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#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
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#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
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#define __PPC_XT(s) __PPC_XS(s)
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#define __PPC_XSP(s) ((((s) & 0x1e) | (((s) >> 5) & 0x1)) << 21)
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#define __PPC_XTP(s) __PPC_XSP(s)
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#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
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#define __PPC_WC(w) (((w) & 0x3) << 21)
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#define __PPC_WS(w) (((w) & 0x1f) << 11)
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#define __PPC_SH(s) __PPC_WS(s)
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#define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4))
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#define __PPC_MB(s) ___PPC_RC(s)
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#define __PPC_ME(s) (((s) & 0x1f) << 1)
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#define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20))
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#define __PPC_ME64(s) __PPC_MB64(s)
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#define __PPC_BI(s) (((s) & 0x1f) << 16)
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#define __PPC_CT(t) (((t) & 0x0f) << 21)
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#define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11))
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#define __PPC_RC21 (0x1 << 10)
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#define __PPC_PRFX_R(r) (((r) & 0x1) << 20)
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/*
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* Both low and high 16 bits are added as SIGNED additions, so if low 16 bits
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* has high bit set, high 16 bits must be adjusted. These macros do that (stolen
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* from binutils).
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*/
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#define PPC_LO(v) ((v) & 0xffff)
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#define PPC_HI(v) (((v) >> 16) & 0xffff)
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#define PPC_HA(v) PPC_HI((v) + 0x8000)
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#define PPC_HIGHER(v) (((v) >> 32) & 0xffff)
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#define PPC_HIGHEST(v) (((v) >> 48) & 0xffff)
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/*
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* Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
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* larx with EH set as an illegal instruction.
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*/
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#ifdef CONFIG_PPC64
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#define __PPC_EH(eh) (((eh) & 0x1) << 0)
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#else
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#define __PPC_EH(eh) 0
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#endif
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/* Base instruction encoding */
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#define PPC_RAW_CP_ABORT (0x7c00068c)
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#define PPC_RAW_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_RAW_DARN(t, l) (0x7c0005e6 | ___PPC_RT(t) | (((l) & 0x3) << 16))
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#define PPC_RAW_DCBAL(a, b) (0x7c2005ec | __PPC_RA(a) | __PPC_RB(b))
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#define PPC_RAW_DCBZL(a, b) (0x7c2007ec | __PPC_RA(a) | __PPC_RB(b))
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#define PPC_RAW_LQARX(t, a, b, eh) (0x7c000228 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
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#define PPC_RAW_LDARX(t, a, b, eh) (0x7c0000a8 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
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#define PPC_RAW_LWARX(t, a, b, eh) (0x7c000028 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
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#define PPC_RAW_PHWSYNC (0x7c8004ac)
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#define PPC_RAW_PLWSYNC (0x7ca004ac)
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#define PPC_RAW_STQCX(t, a, b) (0x7c00016d | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_RAW_MADDHD(t, a, b, c) (0x10000030 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
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#define PPC_RAW_MADDHDU(t, a, b, c) (0x10000031 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
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#define PPC_RAW_MADDLD(t, a, b, c) (0x10000033 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
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#define PPC_RAW_MSGSND(b) (0x7c00019c | ___PPC_RB(b))
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#define PPC_RAW_MSGSYNC (0x7c0006ec)
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#define PPC_RAW_MSGCLR(b) (0x7c0001dc | ___PPC_RB(b))
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#define PPC_RAW_MSGSNDP(b) (0x7c00011c | ___PPC_RB(b))
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#define PPC_RAW_MSGCLRP(b) (0x7c00015c | ___PPC_RB(b))
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#define PPC_RAW_PASTE(a, b) (0x7c20070d | ___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_RAW_POPCNTB(a, s) (PPC_INST_POPCNTB | __PPC_RA(a) | __PPC_RS(s))
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#define PPC_RAW_POPCNTD(a, s) (0x7c0003f4 | __PPC_RA(a) | __PPC_RS(s))
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#define PPC_RAW_POPCNTW(a, s) (0x7c0002f4 | __PPC_RA(a) | __PPC_RS(s))
|
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#define PPC_RAW_RFCI (0x4c000066)
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|
#define PPC_RAW_RFDI (0x4c00004e)
|
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#define PPC_RAW_RFMCI (0x4c00004c)
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#define PPC_RAW_TLBILX(t, a, b) (0x7c000024 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
|
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#define PPC_RAW_WAIT(w) (0x7c00007c | __PPC_WC(w))
|
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#define PPC_RAW_TLBIE(lp, a) (0x7c000264 | ___PPC_RB(a) | ___PPC_RS(lp))
|
|
#define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \
|
|
(0x7c000264 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
|
|
#define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \
|
|
(0x7c000224 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
|
|
#define PPC_RAW_TLBSRX_DOT(a, b) (0x7c0006a5 | __PPC_RA0(a) | __PPC_RB(b))
|
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#define PPC_RAW_TLBIVAX(a, b) (0x7c000624 | __PPC_RA0(a) | __PPC_RB(b))
|
|
#define PPC_RAW_ERATWE(s, a, w) (0x7c0001a6 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
|
|
#define PPC_RAW_ERATRE(s, a, w) (0x7c000166 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
|
|
#define PPC_RAW_ERATILX(t, a, b) (0x7c000066 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
|
|
#define PPC_RAW_ERATIVAX(s, a, b) (0x7c000666 | __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
|
|
#define PPC_RAW_ERATSX(t, a, w) (0x7c000126 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
|
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#define PPC_RAW_ERATSX_DOT(t, a, w) (0x7c000127 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
|
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#define PPC_RAW_SLBFEE_DOT(t, b) (0x7c0007a7 | __PPC_RT(t) | __PPC_RB(b))
|
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#define __PPC_RAW_SLBFEE_DOT(t, b) (0x7c0007a7 | ___PPC_RT(t) | ___PPC_RB(b))
|
|
#define PPC_RAW_ICBT(c, a, b) (0x7c00002c | __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
|
|
#define PPC_RAW_LBZCIX(t, a, b) (0x7c0006aa | __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
|
|
#define PPC_RAW_STBCIX(s, a, b) (0x7c0007aa | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
|
|
#define PPC_RAW_DCBFPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21))
|
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#define PPC_RAW_DCBSTPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21))
|
|
#define PPC_RAW_SC() (0x44000002)
|
|
#define PPC_RAW_SYNC() (0x7c0004ac)
|
|
#define PPC_RAW_ISYNC() (0x4c00012c)
|
|
|
|
/*
|
|
* Define what the VSX XX1 form instructions will look like, then add
|
|
* the 128 bit load store instructions based on that.
|
|
*/
|
|
#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
|
|
#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
|
|
#define PPC_RAW_STXVD2X(s, a, b) (0x7c000798 | VSX_XX1((s), a, b))
|
|
#define PPC_RAW_LXVD2X(s, a, b) (0x7c000698 | VSX_XX1((s), a, b))
|
|
#define PPC_RAW_MFVRD(a, t) (0x7c000066 | VSX_XX1((t) + 32, a, R0))
|
|
#define PPC_RAW_MTVRD(t, a) (0x7c000166 | VSX_XX1((t) + 32, a, R0))
|
|
#define PPC_RAW_VPMSUMW(t, a, b) (0x10000488 | VSX_XX3((t), a, b))
|
|
#define PPC_RAW_VPMSUMD(t, a, b) (0x100004c8 | VSX_XX3((t), a, b))
|
|
#define PPC_RAW_XXLOR(t, a, b) (0xf0000490 | VSX_XX3((t), a, b))
|
|
#define PPC_RAW_XXSWAPD(t, a) (0xf0000250 | VSX_XX3((t), a, a))
|
|
#define PPC_RAW_XVCPSGNDP(t, a, b) ((0xf0000780 | VSX_XX3((t), (a), (b))))
|
|
#define PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc) \
|
|
((0x1000002d | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
|
|
#define PPC_RAW_LXVP(xtp, a, i) (0x18000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_DQ(i))
|
|
#define PPC_RAW_STXVP(xsp, a, i) (0x18000001 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_DQ(i))
|
|
#define PPC_RAW_LXVPX(xtp, a, b) (0x7c00029a | __PPC_XTP(xtp) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_STXVPX(xsp, a, b) (0x7c00039a | __PPC_XSP(xsp) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_PLXVP_P(xtp, i, a, pr) (PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i))
|
|
#define PPC_RAW_PLXVP_S(xtp, i, a, pr) (0xe8000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_D1(i))
|
|
#define PPC_RAW_PSTXVP_P(xsp, i, a, pr) (PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i))
|
|
#define PPC_RAW_PSTXVP_S(xsp, i, a, pr) (0xf8000000 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_D1(i))
|
|
#define PPC_RAW_NAP (0x4c000364)
|
|
#define PPC_RAW_SLEEP (0x4c0003a4)
|
|
#define PPC_RAW_WINKLE (0x4c0003e4)
|
|
#define PPC_RAW_STOP (0x4c0002e4)
|
|
#define PPC_RAW_CLRBHRB (0x7c00035c)
|
|
#define PPC_RAW_MFBHRBE(r, n) (0x7c00025c | __PPC_RT(r) | (((n) & 0x3ff) << 11))
|
|
#define PPC_RAW_TRECHKPT (PPC_INST_TRECHKPT)
|
|
#define PPC_RAW_TRECLAIM(r) (PPC_INST_TRECLAIM | __PPC_RA(r))
|
|
#define PPC_RAW_TABORT(r) (0x7c00071d | __PPC_RA(r))
|
|
#define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
|
|
#define PPC_RAW_MTTMR(tmr, r) (0x7c0003dc | TMRN(tmr) | ___PPC_RS(r))
|
|
#define PPC_RAW_MFTMR(tmr, r) (0x7c0002dc | TMRN(tmr) | ___PPC_RT(r))
|
|
#define PPC_RAW_ICSWX(s, a, b) (0x7c00032d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_ICSWEPX(s, a, b) (0x7c00076d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_SLBIA(IH) (0x7c0003e4 | (((IH) & 0x7) << 21))
|
|
#define PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb) \
|
|
(0x100000c7 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
|
|
#define PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb) \
|
|
(0x10000006 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
|
|
#define PPC_RAW_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i))
|
|
#define PPC_RAW_LWZ(r, base, i) (0x80000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
|
|
#define PPC_RAW_LWZX(t, a, b) (0x7c00002e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_STD(r, base, i) (PPC_INST_STD | ___PPC_RS(r) | ___PPC_RA(base) | IMM_DS(i))
|
|
#define PPC_RAW_STDCX(s, a, b) (0x7c0001ad | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_LFSX(t, a, b) (0x7c00042e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_STFSX(s, a, b) (0x7c00052e | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_LFDX(t, a, b) (0x7c0004ae | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_STFDX(s, a, b) (0x7c0005ae | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_LVX(t, a, b) (0x7c0000ce | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_STVX(s, a, b) (0x7c0001ce | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_ADDE(t, a, b) (0x7c000114 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_ADDZE(t, a) (0x7c000194 | ___PPC_RT(t) | ___PPC_RA(a))
|
|
#define PPC_RAW_ADDME(t, a) (0x7c0001d4 | ___PPC_RT(t) | ___PPC_RA(a))
|
|
#define PPC_RAW_ADD(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_ADD_DOT(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
|
|
#define PPC_RAW_ADDC(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_ADDC_DOT(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
|
|
#define PPC_RAW_NOP() PPC_RAW_ORI(0, 0, 0)
|
|
#define PPC_RAW_BLR() (0x4e800020)
|
|
#define PPC_RAW_BLRL() (0x4e800021)
|
|
#define PPC_RAW_MTLR(r) (0x7c0803a6 | ___PPC_RT(r))
|
|
#define PPC_RAW_MFLR(t) (0x7c0802a6 | ___PPC_RT(t))
|
|
#define PPC_RAW_BCTR() (0x4e800420)
|
|
#define PPC_RAW_BCTRL() (0x4e800421)
|
|
#define PPC_RAW_MTCTR(r) (0x7c0903a6 | ___PPC_RT(r))
|
|
#define PPC_RAW_ADDI(d, a, i) (0x38000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
|
|
#define PPC_RAW_LI(r, i) PPC_RAW_ADDI(r, 0, i)
|
|
#define PPC_RAW_ADDIS(d, a, i) (0x3c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
|
|
#define PPC_RAW_ADDIC(d, a, i) (0x30000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
|
|
#define PPC_RAW_ADDIC_DOT(d, a, i) (0x34000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
|
|
#define PPC_RAW_LIS(r, i) PPC_RAW_ADDIS(r, 0, i)
|
|
#define PPC_RAW_STDX(r, base, b) (0x7c00012a | ___PPC_RS(r) | ___PPC_RA(base) | ___PPC_RB(b))
|
|
#define PPC_RAW_STDU(r, base, i) (0xf8000001 | ___PPC_RS(r) | ___PPC_RA(base) | ((i) & 0xfffc))
|
|
#define PPC_RAW_STW(r, base, i) (0x90000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
|
|
#define PPC_RAW_STWU(r, base, i) (0x94000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
|
|
#define PPC_RAW_STH(r, base, i) (0xb0000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
|
|
#define PPC_RAW_STB(r, base, i) (0x98000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
|
|
#define PPC_RAW_LBZ(r, base, i) (0x88000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
|
|
#define PPC_RAW_LDX(r, base, b) (0x7c00002a | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
|
|
#define PPC_RAW_LHZ(r, base, i) (0xa0000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
|
|
#define PPC_RAW_LHBRX(r, base, b) (0x7c00062c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
|
|
#define PPC_RAW_LDBRX(r, base, b) (0x7c000428 | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
|
|
#define PPC_RAW_STWCX(s, a, b) (0x7c00012d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_CMPWI(a, i) (0x2c000000 | ___PPC_RA(a) | IMM_L(i))
|
|
#define PPC_RAW_CMPDI(a, i) (0x2c200000 | ___PPC_RA(a) | IMM_L(i))
|
|
#define PPC_RAW_CMPW(a, b) (0x7c000000 | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_CMPD(a, b) (0x7c200000 | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_CMPLWI(a, i) (0x28000000 | ___PPC_RA(a) | IMM_L(i))
|
|
#define PPC_RAW_CMPLDI(a, i) (0x28200000 | ___PPC_RA(a) | IMM_L(i))
|
|
#define PPC_RAW_CMPLW(a, b) (0x7c000040 | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_CMPLD(a, b) (0x7c200040 | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_SUB(d, a, b) (0x7c000050 | ___PPC_RT(d) | ___PPC_RB(a) | ___PPC_RA(b))
|
|
#define PPC_RAW_SUBFC(d, a, b) (0x7c000010 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_SUBFE(d, a, b) (0x7c000110 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_SUBFIC(d, a, i) (0x20000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
|
|
#define PPC_RAW_SUBFZE(d, a) (0x7c000190 | ___PPC_RT(d) | ___PPC_RA(a))
|
|
#define PPC_RAW_MULD(d, a, b) (0x7c0001d2 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_MULW(d, a, b) (0x7c0001d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_MULHWU(d, a, b) (0x7c000016 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_MULI(d, a, i) (0x1c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
|
|
#define PPC_RAW_DIVWU(d, a, b) (0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_DIVDU(d, a, b) (0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_DIVDE(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_DIVDE_DOT(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
|
|
#define PPC_RAW_DIVDEU(t, a, b) (0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_DIVDEU_DOT(t, a, b) (0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
|
|
#define PPC_RAW_AND(d, a, b) (0x7c000038 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_ANDI(d, a, i) (0x70000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
|
|
#define PPC_RAW_ANDIS(d, a, i) (0x74000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
|
|
#define PPC_RAW_AND_DOT(d, a, b) (0x7c000039 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_OR(d, a, b) (0x7c000378 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_MR(d, a) PPC_RAW_OR(d, a, a)
|
|
#define PPC_RAW_ORI(d, a, i) (0x60000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
|
|
#define PPC_RAW_ORIS(d, a, i) (0x64000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
|
|
#define PPC_RAW_NOR(d, a, b) (0x7c0000f8 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_XOR(d, a, b) (0x7c000278 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
|
|
#define PPC_RAW_XORI(d, a, i) (0x68000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
|
|
#define PPC_RAW_XORIS(d, a, i) (0x6c000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
|
|
#define PPC_RAW_EXTSW(d, a) (0x7c0007b4 | ___PPC_RA(d) | ___PPC_RS(a))
|
|
#define PPC_RAW_SLW(d, a, s) (0x7c000030 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
|
|
#define PPC_RAW_SLD(d, a, s) (0x7c000036 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
|
|
#define PPC_RAW_SRW(d, a, s) (0x7c000430 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
|
|
#define PPC_RAW_SRAW(d, a, s) (0x7c000630 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
|
|
#define PPC_RAW_SRAWI(d, a, i) (0x7c000670 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i))
|
|
#define PPC_RAW_SRD(d, a, s) (0x7c000436 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
|
|
#define PPC_RAW_SRAD(d, a, s) (0x7c000634 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
|
|
#define PPC_RAW_SRADI(d, a, i) (0x7c000674 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i))
|
|
#define PPC_RAW_RLWINM(d, a, i, mb, me) (0x54000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
|
|
#define PPC_RAW_RLWINM_DOT(d, a, i, mb, me) \
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(0x54000001 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
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#define PPC_RAW_RLWIMI(d, a, i, mb, me) (0x50000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
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#define PPC_RAW_RLDICL(d, a, i, mb) (0x78000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_MB64(mb))
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#define PPC_RAW_RLDICR(d, a, i, me) (0x78000004 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_ME64(me))
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/* slwi = rlwinm Rx, Ry, n, 0, 31-n */
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#define PPC_RAW_SLWI(d, a, i) PPC_RAW_RLWINM(d, a, i, 0, 31-(i))
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/* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
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#define PPC_RAW_SRWI(d, a, i) PPC_RAW_RLWINM(d, a, 32-(i), i, 31)
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/* sldi = rldicr Rx, Ry, n, 63-n */
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#define PPC_RAW_SLDI(d, a, i) PPC_RAW_RLDICR(d, a, i, 63-(i))
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/* sldi = rldicl Rx, Ry, 64-n, n */
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#define PPC_RAW_SRDI(d, a, i) PPC_RAW_RLDICL(d, a, 64-(i), i)
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#define PPC_RAW_NEG(d, a) (0x7c0000d0 | ___PPC_RT(d) | ___PPC_RA(a))
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#define PPC_RAW_MFSPR(d, spr) (0x7c0002a6 | ___PPC_RT(d) | __PPC_SPR(spr))
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#define PPC_RAW_MTSPR(spr, d) (0x7c0003a6 | ___PPC_RS(d) | __PPC_SPR(spr))
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#define PPC_RAW_EIEIO() (0x7c0006ac)
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/* Deal with instructions that older assemblers aren't aware of */
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#define PPC_BCCTR_FLUSH stringify_in_c(.long PPC_INST_BCCTR_FLUSH)
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#define PPC_CP_ABORT stringify_in_c(.long PPC_RAW_CP_ABORT)
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#define PPC_COPY(a, b) stringify_in_c(.long PPC_RAW_COPY(a, b))
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#define PPC_DARN(t, l) stringify_in_c(.long PPC_RAW_DARN(t, l))
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#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_RAW_DCBAL(a, b))
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#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_RAW_DCBZL(a, b))
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#define PPC_DIVDE(t, a, b) stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))
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#define PPC_DIVDEU(t, a, b) stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))
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#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))
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#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LDARX(t, a, b, eh))
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#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LWARX(t, a, b, eh))
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#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_RAW_STQCX(t, a, b))
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#define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))
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#define PPC_MADDHDU(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHDU(t, a, b, c))
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#define PPC_MADDLD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDLD(t, a, b, c))
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#define PPC_MSGSND(b) stringify_in_c(.long PPC_RAW_MSGSND(b))
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#define PPC_MSGSYNC stringify_in_c(.long PPC_RAW_MSGSYNC)
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#define PPC_MSGCLR(b) stringify_in_c(.long PPC_RAW_MSGCLR(b))
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#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_RAW_MSGSNDP(b))
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#define PPC_MSGCLRP(b) stringify_in_c(.long PPC_RAW_MSGCLRP(b))
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#define PPC_PASTE(a, b) stringify_in_c(.long PPC_RAW_PASTE(a, b))
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#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_RAW_POPCNTB(a, s))
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#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_RAW_POPCNTD(a, s))
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#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_RAW_POPCNTW(a, s))
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#define PPC_RFCI stringify_in_c(.long PPC_RAW_RFCI)
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#define PPC_RFDI stringify_in_c(.long PPC_RAW_RFDI)
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#define PPC_RFMCI stringify_in_c(.long PPC_RAW_RFMCI)
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#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_RAW_TLBILX(t, a, b))
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#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
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#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
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#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
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#define PPC_WAIT(w) stringify_in_c(.long PPC_RAW_WAIT(w))
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#define PPC_TLBIE(lp, a) stringify_in_c(.long PPC_RAW_TLBIE(lp, a))
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#define PPC_TLBIE_5(rb, rs, ric, prs, r) \
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stringify_in_c(.long PPC_RAW_TLBIE_5(rb, rs, ric, prs, r))
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#define PPC_TLBIEL(rb,rs,ric,prs,r) \
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stringify_in_c(.long PPC_RAW_TLBIEL(rb, rs, ric, prs, r))
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#define PPC_TLBSRX_DOT(a, b) stringify_in_c(.long PPC_RAW_TLBSRX_DOT(a, b))
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#define PPC_TLBIVAX(a, b) stringify_in_c(.long PPC_RAW_TLBIVAX(a, b))
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#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_RAW_ERATWE(s, a, w))
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#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_RAW_ERATRE(a, a, w))
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#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_RAW_ERATILX(t, a, b))
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#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_RAW_ERATIVAX(s, a, b))
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#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_RAW_ERATSX(t, a, w))
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#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_RAW_ERATSX_DOT(t, a, w))
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#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_RAW_SLBFEE_DOT(t, b))
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#define __PPC_SLBFEE_DOT(t, b) stringify_in_c(.long __PPC_RAW_SLBFEE_DOT(t, b))
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#define PPC_ICBT(c, a, b) stringify_in_c(.long PPC_RAW_ICBT(c, a, b))
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/* PASemi instructions */
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#define LBZCIX(t, a, b) stringify_in_c(.long PPC_RAW_LBZCIX(t, a, b))
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#define STBCIX(s, a, b) stringify_in_c(.long PPC_RAW_STBCIX(s, a, b))
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#define PPC_DCBFPS(a, b) stringify_in_c(.long PPC_RAW_DCBFPS(a, b))
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#define PPC_DCBSTPS(a, b) stringify_in_c(.long PPC_RAW_DCBSTPS(a, b))
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#define PPC_PHWSYNC stringify_in_c(.long PPC_RAW_PHWSYNC)
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#define PPC_PLWSYNC stringify_in_c(.long PPC_RAW_PLWSYNC)
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#define STXVD2X(s, a, b) stringify_in_c(.long PPC_RAW_STXVD2X(s, a, b))
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#define LXVD2X(s, a, b) stringify_in_c(.long PPC_RAW_LXVD2X(s, a, b))
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#define MFVRD(a, t) stringify_in_c(.long PPC_RAW_MFVRD(a, t))
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#define MTVRD(t, a) stringify_in_c(.long PPC_RAW_MTVRD(t, a))
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#define VPMSUMW(t, a, b) stringify_in_c(.long PPC_RAW_VPMSUMW(t, a, b))
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#define VPMSUMD(t, a, b) stringify_in_c(.long PPC_RAW_VPMSUMD(t, a, b))
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#define XXLOR(t, a, b) stringify_in_c(.long PPC_RAW_XXLOR(t, a, b))
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#define XXSWAPD(t, a) stringify_in_c(.long PPC_RAW_XXSWAPD(t, a))
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#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_RAW_XVCPSGNDP(t, a, b)))
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#define VPERMXOR(vrt, vra, vrb, vrc) \
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stringify_in_c(.long (PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc)))
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#define PPC_NAP stringify_in_c(.long PPC_RAW_NAP)
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#define PPC_SLEEP stringify_in_c(.long PPC_RAW_SLEEP)
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#define PPC_WINKLE stringify_in_c(.long PPC_RAW_WINKLE)
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#define PPC_STOP stringify_in_c(.long PPC_RAW_STOP)
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/* BHRB instructions */
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#define PPC_CLRBHRB stringify_in_c(.long PPC_RAW_CLRBHRB)
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#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_RAW_MFBHRBE(r, n))
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/* Transactional memory instructions */
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#define TRECHKPT stringify_in_c(.long PPC_RAW_TRECHKPT)
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#define TRECLAIM(r) stringify_in_c(.long PPC_RAW_TRECLAIM(r))
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#define TABORT(r) stringify_in_c(.long PPC_RAW_TABORT(r))
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/* book3e thread control instructions */
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#define MTTMR(tmr, r) stringify_in_c(.long PPC_RAW_MTTMR(tmr, r))
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#define MFTMR(tmr, r) stringify_in_c(.long PPC_RAW_MFTMR(tmr, r))
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/* Coprocessor instructions */
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#define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_RAW_ICSWX(s, a, b))
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#define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_RAW_ICSWEPX(s, a, b))
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#define PPC_SLBIA(IH) stringify_in_c(.long PPC_RAW_SLBIA(IH))
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/*
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* These may only be used on ISA v3.0 or later (aka. CPU_FTR_ARCH_300, radix
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* implies CPU_FTR_ARCH_300). USER/GUEST invalidates may only be used by radix
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* mode (on HPT these would also invalidate various SLBEs which may not be
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* desired).
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*/
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#define PPC_ISA_3_0_INVALIDATE_ERAT PPC_SLBIA(7)
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#define PPC_RADIX_INVALIDATE_ERAT_USER PPC_SLBIA(3)
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#define PPC_RADIX_INVALIDATE_ERAT_GUEST PPC_SLBIA(6)
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#define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb))
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#define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb))
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#endif /* _ASM_POWERPC_PPC_OPCODE_H */
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