187 строки
4.6 KiB
C
187 строки
4.6 KiB
C
/*
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* Copyright (c) 2013 Linaro Ltd.
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* Copyright (c) 2013 Hisilicon Limited.
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* Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/mach/map.h>
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#include "core.h"
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#define HIX5HD2_BOOT_ADDRESS 0xffff0000
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static void __iomem *ctrl_base;
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void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
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{
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cpu = cpu_logical_map(cpu);
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if (!cpu || !ctrl_base)
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return;
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writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2));
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}
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int hi3xxx_get_cpu_jump(int cpu)
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{
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cpu = cpu_logical_map(cpu);
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if (!cpu || !ctrl_base)
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return 0;
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return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
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}
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static void __init hisi_enable_scu_a9(void)
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{
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unsigned long base = 0;
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void __iomem *scu_base = NULL;
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if (scu_a9_has_base()) {
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base = scu_a9_get_base();
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scu_base = ioremap(base, SZ_4K);
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if (!scu_base) {
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pr_err("ioremap(scu_base) failed\n");
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return;
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}
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scu_enable(scu_base);
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iounmap(scu_base);
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}
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}
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static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np = NULL;
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u32 offset = 0;
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hisi_enable_scu_a9();
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if (!ctrl_base) {
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np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
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if (!np) {
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pr_err("failed to find hisilicon,sysctrl node\n");
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return;
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}
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ctrl_base = of_iomap(np, 0);
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if (!ctrl_base) {
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pr_err("failed to map address\n");
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return;
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}
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if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
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pr_err("failed to find smp-offset property\n");
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return;
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}
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ctrl_base += offset;
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}
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}
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static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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hi3xxx_set_cpu(cpu, true);
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hi3xxx_set_cpu_jump(cpu, secondary_startup);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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static const struct smp_operations hi3xxx_smp_ops __initconst = {
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.smp_prepare_cpus = hi3xxx_smp_prepare_cpus,
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.smp_boot_secondary = hi3xxx_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = hi3xxx_cpu_die,
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.cpu_kill = hi3xxx_cpu_kill,
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#endif
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};
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static void __init hisi_common_smp_prepare_cpus(unsigned int max_cpus)
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{
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hisi_enable_scu_a9();
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}
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static void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
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{
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void __iomem *virt;
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virt = ioremap(start_addr, PAGE_SIZE);
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writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */
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writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */
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iounmap(virt);
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}
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static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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phys_addr_t jumpaddr;
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jumpaddr = __pa_symbol(secondary_startup);
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hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
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hix5hd2_set_cpu(cpu, true);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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static const struct smp_operations hix5hd2_smp_ops __initconst = {
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.smp_prepare_cpus = hisi_common_smp_prepare_cpus,
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.smp_boot_secondary = hix5hd2_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = hix5hd2_cpu_die,
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#endif
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};
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#define SC_SCTL_REMAP_CLR 0x00000100
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#define HIP01_BOOT_ADDRESS 0x80000000
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#define REG_SC_CTRL 0x000
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static void hip01_set_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
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{
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void __iomem *virt;
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virt = phys_to_virt(start_addr);
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writel_relaxed(0xe51ff004, virt);
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writel_relaxed(jump_addr, virt + 4);
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}
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static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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phys_addr_t jumpaddr;
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unsigned int remap_reg_value = 0;
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struct device_node *node;
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jumpaddr = __pa_symbol(secondary_startup);
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hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
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node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
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if (WARN_ON(!node))
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return -1;
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ctrl_base = of_iomap(node, 0);
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/* set the secondary core boot from DDR */
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remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL);
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barrier();
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remap_reg_value |= SC_SCTL_REMAP_CLR;
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barrier();
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writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL);
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hip01_set_cpu(cpu, true);
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return 0;
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}
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static const struct smp_operations hip01_smp_ops __initconst = {
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.smp_prepare_cpus = hisi_common_smp_prepare_cpus,
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.smp_boot_secondary = hip01_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
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CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);
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CPU_METHOD_OF_DECLARE(hip01_smp, "hisilicon,hip01-smp", &hip01_smp_ops);
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