199 строки
5.3 KiB
C
199 строки
5.3 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König <christian.koenig@amd.com>
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "rv770d.h"
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/**
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* uvd_v2_2_fence_emit - emit an fence & trap command
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*
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* @rdev: radeon_device pointer
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* @fence: fence to emit
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*
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* Write a fence and a trap command to the ring.
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*/
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void uvd_v2_2_fence_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
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radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
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radeon_ring_write(ring, fence->seq);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
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radeon_ring_write(ring, lower_32_bits(addr));
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
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radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
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radeon_ring_write(ring, 2);
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}
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/**
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* uvd_v2_2_semaphore_emit - emit semaphore command
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring pointer
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* @semaphore: semaphore to emit commands for
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* @emit_wait: true if we should emit a wait command
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*
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* Emit a semaphore command (either wait or signal) to the UVD ring.
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*/
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bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
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struct radeon_ring *ring,
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struct radeon_semaphore *semaphore,
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bool emit_wait)
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{
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uint64_t addr = semaphore->gpu_addr;
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radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
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radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
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radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
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radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
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radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
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radeon_ring_write(ring, emit_wait ? 1 : 0);
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return true;
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}
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/**
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* uvd_v2_2_resume - memory controller programming
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*
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* @rdev: radeon_device pointer
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*
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* Let the UVD memory controller know it's offsets
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*/
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int uvd_v2_2_resume(struct radeon_device *rdev)
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{
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uint64_t addr;
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uint32_t chip_id, size;
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int r;
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/* RV770 uses V1.0 MC */
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if (rdev->family == CHIP_RV770)
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return uvd_v1_0_resume(rdev);
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r = radeon_uvd_resume(rdev);
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if (r)
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return r;
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/* programm the VCPU memory controller bits 0-27 */
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addr = rdev->uvd.gpu_addr >> 3;
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size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
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WREG32(UVD_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = RADEON_UVD_STACK_SIZE >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
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WREG32(UVD_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = RADEON_UVD_HEAP_SIZE >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
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WREG32(UVD_VCPU_CACHE_SIZE2, size);
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/* bits 28-31 */
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addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
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WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
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/* bits 32-39 */
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addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
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WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
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/* tell firmware which hardware it is running on */
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switch (rdev->family) {
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default:
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return -EINVAL;
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case CHIP_RV710:
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chip_id = 0x01000005;
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break;
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case CHIP_RV730:
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chip_id = 0x01000006;
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break;
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case CHIP_RV740:
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chip_id = 0x01000007;
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break;
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case CHIP_CYPRESS:
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case CHIP_HEMLOCK:
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chip_id = 0x01000008;
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break;
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case CHIP_JUNIPER:
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chip_id = 0x01000009;
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break;
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case CHIP_REDWOOD:
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chip_id = 0x0100000a;
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break;
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case CHIP_CEDAR:
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chip_id = 0x0100000b;
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break;
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case CHIP_SUMO:
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case CHIP_SUMO2:
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chip_id = 0x0100000c;
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break;
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case CHIP_PALM:
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chip_id = 0x0100000e;
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break;
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case CHIP_CAYMAN:
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chip_id = 0x0100000f;
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break;
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case CHIP_BARTS:
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chip_id = 0x01000010;
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break;
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case CHIP_TURKS:
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chip_id = 0x01000011;
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break;
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case CHIP_CAICOS:
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chip_id = 0x01000012;
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break;
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case CHIP_TAHITI:
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chip_id = 0x01000014;
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break;
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case CHIP_VERDE:
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chip_id = 0x01000015;
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break;
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case CHIP_PITCAIRN:
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case CHIP_OLAND:
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chip_id = 0x01000016;
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break;
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case CHIP_ARUBA:
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chip_id = 0x01000017;
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break;
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}
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WREG32(UVD_VCPU_CHIP_ID, chip_id);
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return 0;
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}
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