899 строки
25 KiB
ArmAsm
899 строки
25 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Low-level CPU initialisation
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* Based on arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (C) 2003-2012 ARM Ltd.
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* Authors: Catalin Marinas <catalin.marinas@arm.com>
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* Will Deacon <will.deacon@arm.com>
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/pgtable.h>
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#include <asm/asm_pointer_auth.h>
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#include <asm/assembler.h>
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#include <asm/boot.h>
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#include <asm/bug.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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#include <asm/cputype.h>
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#include <asm/el2_setup.h>
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#include <asm/elf.h>
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#include <asm/image.h>
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#include <asm/kernel-pgtable.h>
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#include <asm/kvm_arm.h>
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#include <asm/memory.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/page.h>
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#include <asm/scs.h>
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#include <asm/smp.h>
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#include <asm/sysreg.h>
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#include <asm/thread_info.h>
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#include <asm/virt.h>
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#include "efi-header.S"
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#define __PHYS_OFFSET KERNEL_START
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#if (PAGE_OFFSET & 0x1fffff) != 0
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#error PAGE_OFFSET must be at least 2MB aligned
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#endif
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* The requirements are:
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* MMU = off, D-cache = off, I-cache = on or off,
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* x0 = physical address to the FDT blob.
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*
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* This code is mostly position independent so you call this at
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* __pa(PAGE_OFFSET).
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*
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* Note that the callee-saved registers are used for storing variables
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* that are useful before the MMU is enabled. The allocations are described
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* in the entry routines.
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*/
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__HEAD
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/*
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* DO NOT MODIFY. Image header expected by Linux boot-loaders.
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*/
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efi_signature_nop // special NOP to identity as PE/COFF executable
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b primary_entry // branch to kernel start, magic
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.quad 0 // Image load offset from start of RAM, little-endian
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le64sym _kernel_size_le // Effective size of kernel image, little-endian
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le64sym _kernel_flags_le // Informative flags, little-endian
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.quad 0 // reserved
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.quad 0 // reserved
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.quad 0 // reserved
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.ascii ARM64_IMAGE_MAGIC // Magic number
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.long .Lpe_header_offset // Offset to the PE header.
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__EFI_PE_HEADER
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__INIT
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/*
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* The following callee saved general purpose registers are used on the
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* primary lowlevel boot path:
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*
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* Register Scope Purpose
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* x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0
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* x23 primary_entry() .. start_kernel() physical misalignment/KASLR offset
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* x28 __create_page_tables() callee preserved temp register
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* x19/x20 __primary_switch() callee preserved temp registers
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* x24 __primary_switch() .. relocate_kernel() current RELR displacement
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*/
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SYM_CODE_START(primary_entry)
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bl preserve_boot_args
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bl init_kernel_el // w0=cpu_boot_mode
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adrp x23, __PHYS_OFFSET
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and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
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bl set_cpu_boot_mode_flag
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bl __create_page_tables
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/*
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* The following calls CPU setup code, see arch/arm64/mm/proc.S for
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* details.
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* On return, the CPU will be ready for the MMU to be turned on and
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* the TCR will have been set.
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*/
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bl __cpu_setup // initialise processor
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b __primary_switch
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SYM_CODE_END(primary_entry)
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/*
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* Preserve the arguments passed by the bootloader in x0 .. x3
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*/
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SYM_CODE_START_LOCAL(preserve_boot_args)
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mov x21, x0 // x21=FDT
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adr_l x0, boot_args // record the contents of
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stp x21, x1, [x0] // x0 .. x3 at kernel entry
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stp x2, x3, [x0, #16]
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dmb sy // needed before dc ivac with
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// MMU off
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add x1, x0, #0x20 // 4 x 8 bytes
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b dcache_inval_poc // tail call
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SYM_CODE_END(preserve_boot_args)
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/*
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* Macro to create a table entry to the next page.
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*
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* tbl: page table address
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* virt: virtual address
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* shift: #imm page table shift
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* ptrs: #imm pointers per table page
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*
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* Preserves: virt
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* Corrupts: ptrs, tmp1, tmp2
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* Returns: tbl -> next level table page address
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*/
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.macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
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add \tmp1, \tbl, #PAGE_SIZE
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phys_to_pte \tmp2, \tmp1
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orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
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lsr \tmp1, \virt, #\shift
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sub \ptrs, \ptrs, #1
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and \tmp1, \tmp1, \ptrs // table index
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str \tmp2, [\tbl, \tmp1, lsl #3]
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add \tbl, \tbl, #PAGE_SIZE // next level table page
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.endm
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/*
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* Macro to populate page table entries, these entries can be pointers to the next level
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* or last level entries pointing to physical memory.
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*
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* tbl: page table address
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* rtbl: pointer to page table or physical memory
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* index: start index to write
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* eindex: end index to write - [index, eindex] written to
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* flags: flags for pagetable entry to or in
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* inc: increment to rtbl between each entry
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* tmp1: temporary variable
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*
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* Preserves: tbl, eindex, flags, inc
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* Corrupts: index, tmp1
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* Returns: rtbl
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*/
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.macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
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.Lpe\@: phys_to_pte \tmp1, \rtbl
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orr \tmp1, \tmp1, \flags // tmp1 = table entry
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str \tmp1, [\tbl, \index, lsl #3]
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add \rtbl, \rtbl, \inc // rtbl = pa next level
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add \index, \index, #1
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cmp \index, \eindex
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b.ls .Lpe\@
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.endm
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/*
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* Compute indices of table entries from virtual address range. If multiple entries
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* were needed in the previous page table level then the next page table level is assumed
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* to be composed of multiple pages. (This effectively scales the end index).
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*
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* vstart: virtual address of start of range
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* vend: virtual address of end of range - we map [vstart, vend]
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* shift: shift used to transform virtual address into index
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* ptrs: number of entries in page table
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* istart: index in table corresponding to vstart
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* iend: index in table corresponding to vend
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* count: On entry: how many extra entries were required in previous level, scales
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* our end index.
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* On exit: returns how many extra entries required for next page table level
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*
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* Preserves: vstart, vend, shift, ptrs
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* Returns: istart, iend, count
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*/
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.macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count
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lsr \iend, \vend, \shift
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mov \istart, \ptrs
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sub \istart, \istart, #1
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and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1)
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mov \istart, \ptrs
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mul \istart, \istart, \count
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add \iend, \iend, \istart // iend += count * ptrs
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// our entries span multiple tables
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lsr \istart, \vstart, \shift
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mov \count, \ptrs
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sub \count, \count, #1
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and \istart, \istart, \count
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sub \count, \iend, \istart
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.endm
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/*
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* Map memory for specified virtual address range. Each level of page table needed supports
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* multiple entries. If a level requires n entries the next page table level is assumed to be
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* formed from n pages.
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*
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* tbl: location of page table
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* rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
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* vstart: virtual address of start of range
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* vend: virtual address of end of range - we map [vstart, vend - 1]
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* flags: flags to use to map last level entries
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* phys: physical address corresponding to vstart - physical memory is contiguous
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* pgds: the number of pgd entries
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*
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* Temporaries: istart, iend, tmp, count, sv - these need to be different registers
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* Preserves: vstart, flags
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* Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv
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*/
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.macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
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sub \vend, \vend, #1
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add \rtbl, \tbl, #PAGE_SIZE
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mov \sv, \rtbl
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mov \count, #0
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compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count
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populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
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mov \tbl, \sv
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mov \sv, \rtbl
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#if SWAPPER_PGTABLE_LEVELS > 3
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compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count
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populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
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mov \tbl, \sv
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mov \sv, \rtbl
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#endif
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#if SWAPPER_PGTABLE_LEVELS > 2
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compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count
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populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
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mov \tbl, \sv
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#endif
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compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count
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bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1
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populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp
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.endm
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/*
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* Setup the initial page tables. We only setup the barest amount which is
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* required to get the kernel running. The following sections are required:
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* - identity mapping to enable the MMU (low address, TTBR0)
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* - first few MB of the kernel linear mapping to jump to once the MMU has
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* been enabled
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*/
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SYM_FUNC_START_LOCAL(__create_page_tables)
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mov x28, lr
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/*
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* Invalidate the init page tables to avoid potential dirty cache lines
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* being evicted. Other page tables are allocated in rodata as part of
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* the kernel image, and thus are clean to the PoC per the boot
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* protocol.
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*/
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adrp x0, init_pg_dir
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adrp x1, init_pg_end
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bl dcache_inval_poc
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/*
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* Clear the init page tables.
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*/
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adrp x0, init_pg_dir
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adrp x1, init_pg_end
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sub x1, x1, x0
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1: stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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subs x1, x1, #64
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b.ne 1b
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mov x7, SWAPPER_MM_MMUFLAGS
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/*
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* Create the identity mapping.
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*/
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adrp x0, idmap_pg_dir
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adrp x3, __idmap_text_start // __pa(__idmap_text_start)
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#ifdef CONFIG_ARM64_VA_BITS_52
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mrs_s x6, SYS_ID_AA64MMFR2_EL1
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and x6, x6, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
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mov x5, #52
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cbnz x6, 1f
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#endif
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mov x5, #VA_BITS_MIN
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1:
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adr_l x6, vabits_actual
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str x5, [x6]
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dmb sy
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dc ivac, x6 // Invalidate potentially stale cache line
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/*
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* VA_BITS may be too small to allow for an ID mapping to be created
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* that covers system RAM if that is located sufficiently high in the
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* physical address space. So for the ID map, use an extended virtual
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* range in that case, and configure an additional translation level
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* if needed.
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*
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* Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
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* entire ID map region can be mapped. As T0SZ == (64 - #bits used),
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* this number conveniently equals the number of leading zeroes in
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* the physical address of __idmap_text_end.
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*/
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adrp x5, __idmap_text_end
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clz x5, x5
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cmp x5, TCR_T0SZ(VA_BITS_MIN) // default T0SZ small enough?
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b.ge 1f // .. then skip VA range extension
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adr_l x6, idmap_t0sz
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str x5, [x6]
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dmb sy
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dc ivac, x6 // Invalidate potentially stale cache line
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#if (VA_BITS < 48)
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#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
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#define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT))
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/*
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* If VA_BITS < 48, we have to configure an additional table level.
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* First, we have to verify our assumption that the current value of
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* VA_BITS was chosen such that all translation levels are fully
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* utilised, and that lowering T0SZ will always result in an additional
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* translation level to be configured.
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*/
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#if VA_BITS != EXTRA_SHIFT
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#error "Mismatch between VA_BITS and page size/number of translation levels"
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#endif
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mov x4, EXTRA_PTRS
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create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6
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#else
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/*
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* If VA_BITS == 48, we don't have to configure an additional
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* translation level, but the top-level table has more entries.
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*/
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mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)
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str_l x4, idmap_ptrs_per_pgd, x5
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#endif
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1:
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ldr_l x4, idmap_ptrs_per_pgd
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adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
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map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14
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/*
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* Map the kernel image (starting with PHYS_OFFSET).
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*/
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adrp x0, init_pg_dir
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mov_q x5, KIMAGE_VADDR // compile time __va(_text)
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add x5, x5, x23 // add KASLR displacement
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mov x4, PTRS_PER_PGD
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adrp x6, _end // runtime __pa(_end)
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adrp x3, _text // runtime __pa(_text)
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sub x6, x6, x3 // _end - _text
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add x6, x6, x5 // runtime __va(_end)
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map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14
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/*
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* Since the page tables have been populated with non-cacheable
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* accesses (MMU disabled), invalidate those tables again to
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* remove any speculatively loaded cache lines.
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*/
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dmb sy
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adrp x0, idmap_pg_dir
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adrp x1, idmap_pg_end
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bl dcache_inval_poc
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adrp x0, init_pg_dir
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adrp x1, init_pg_end
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bl dcache_inval_poc
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ret x28
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SYM_FUNC_END(__create_page_tables)
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/*
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* Initialize CPU registers with task-specific and cpu-specific context.
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*
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* Create a final frame record at task_pt_regs(current)->stackframe, so
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* that the unwinder can identify the final frame record of any task by
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* its location in the task stack. We reserve the entire pt_regs space
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* for consistency with user tasks and kthreads.
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*/
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.macro init_cpu_task tsk, tmp1, tmp2
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msr sp_el0, \tsk
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ldr \tmp1, [\tsk, #TSK_STACK]
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add sp, \tmp1, #THREAD_SIZE
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sub sp, sp, #PT_REGS_SIZE
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stp xzr, xzr, [sp, #S_STACKFRAME]
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add x29, sp, #S_STACKFRAME
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scs_load \tsk
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adr_l \tmp1, __per_cpu_offset
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ldr w\tmp2, [\tsk, #TSK_TI_CPU]
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ldr \tmp1, [\tmp1, \tmp2, lsl #3]
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set_this_cpu_offset \tmp1
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.endm
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/*
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* The following fragment of code is executed with the MMU enabled.
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*
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* x0 = __PHYS_OFFSET
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*/
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SYM_FUNC_START_LOCAL(__primary_switched)
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adr_l x4, init_task
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init_cpu_task x4, x5, x6
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adr_l x8, vectors // load VBAR_EL1 with virtual
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msr vbar_el1, x8 // vector table address
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isb
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stp x29, x30, [sp, #-16]!
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mov x29, sp
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str_l x21, __fdt_pointer, x5 // Save FDT pointer
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ldr_l x4, kimage_vaddr // Save the offset between
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sub x4, x4, x0 // the kernel virtual and
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str_l x4, kimage_voffset, x5 // physical mappings
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// Clear BSS
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adr_l x0, __bss_start
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mov x1, xzr
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adr_l x2, __bss_stop
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sub x2, x2, x0
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bl __pi_memset
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dsb ishst // Make zero page visible to PTW
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#if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
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bl kasan_early_init
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#endif
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mov x0, x21 // pass FDT address in x0
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bl early_fdt_map // Try mapping the FDT early
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bl init_feature_override // Parse cpu feature overrides
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#ifdef CONFIG_RANDOMIZE_BASE
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tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized?
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b.ne 0f
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bl kaslr_early_init // parse FDT for KASLR options
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cbz x0, 0f // KASLR disabled? just proceed
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orr x23, x23, x0 // record KASLR offset
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ldp x29, x30, [sp], #16 // we must enable KASLR, return
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ret // to __primary_switch()
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0:
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#endif
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bl switch_to_vhe // Prefer VHE if possible
|
|
ldp x29, x30, [sp], #16
|
|
bl start_kernel
|
|
ASM_BUG()
|
|
SYM_FUNC_END(__primary_switched)
|
|
|
|
.pushsection ".rodata", "a"
|
|
SYM_DATA_START(kimage_vaddr)
|
|
.quad _text
|
|
SYM_DATA_END(kimage_vaddr)
|
|
EXPORT_SYMBOL(kimage_vaddr)
|
|
.popsection
|
|
|
|
/*
|
|
* end early head section, begin head code that is also used for
|
|
* hotplug and needs to have the same protections as the text region
|
|
*/
|
|
.section ".idmap.text","awx"
|
|
|
|
/*
|
|
* Starting from EL2 or EL1, configure the CPU to execute at the highest
|
|
* reachable EL supported by the kernel in a chosen default state. If dropping
|
|
* from EL2 to EL1, configure EL2 before configuring EL1.
|
|
*
|
|
* Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if
|
|
* SCTLR_ELx.EOS is clear), we place an ISB prior to ERET.
|
|
*
|
|
* Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if
|
|
* booted in EL1 or EL2 respectively.
|
|
*/
|
|
SYM_FUNC_START(init_kernel_el)
|
|
mrs x0, CurrentEL
|
|
cmp x0, #CurrentEL_EL2
|
|
b.eq init_el2
|
|
|
|
SYM_INNER_LABEL(init_el1, SYM_L_LOCAL)
|
|
mov_q x0, INIT_SCTLR_EL1_MMU_OFF
|
|
msr sctlr_el1, x0
|
|
isb
|
|
mov_q x0, INIT_PSTATE_EL1
|
|
msr spsr_el1, x0
|
|
msr elr_el1, lr
|
|
mov w0, #BOOT_CPU_MODE_EL1
|
|
eret
|
|
|
|
SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
|
|
mov_q x0, HCR_HOST_NVHE_FLAGS
|
|
msr hcr_el2, x0
|
|
isb
|
|
|
|
init_el2_state
|
|
|
|
/* Hypervisor stub */
|
|
adr_l x0, __hyp_stub_vectors
|
|
msr vbar_el2, x0
|
|
isb
|
|
|
|
/*
|
|
* Fruity CPUs seem to have HCR_EL2.E2H set to RES1,
|
|
* making it impossible to start in nVHE mode. Is that
|
|
* compliant with the architecture? Absolutely not!
|
|
*/
|
|
mrs x0, hcr_el2
|
|
and x0, x0, #HCR_E2H
|
|
cbz x0, 1f
|
|
|
|
/* Switching to VHE requires a sane SCTLR_EL1 as a start */
|
|
mov_q x0, INIT_SCTLR_EL1_MMU_OFF
|
|
msr_s SYS_SCTLR_EL12, x0
|
|
|
|
/*
|
|
* Force an eret into a helper "function", and let it return
|
|
* to our original caller... This makes sure that we have
|
|
* initialised the basic PSTATE state.
|
|
*/
|
|
mov x0, #INIT_PSTATE_EL2
|
|
msr spsr_el1, x0
|
|
adr x0, __cpu_stick_to_vhe
|
|
msr elr_el1, x0
|
|
eret
|
|
|
|
1:
|
|
mov_q x0, INIT_SCTLR_EL1_MMU_OFF
|
|
msr sctlr_el1, x0
|
|
|
|
msr elr_el2, lr
|
|
mov w0, #BOOT_CPU_MODE_EL2
|
|
eret
|
|
|
|
__cpu_stick_to_vhe:
|
|
mov x0, #HVC_VHE_RESTART
|
|
hvc #0
|
|
mov x0, #BOOT_CPU_MODE_EL2
|
|
ret
|
|
SYM_FUNC_END(init_kernel_el)
|
|
|
|
/*
|
|
* Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
|
|
* in w0. See arch/arm64/include/asm/virt.h for more info.
|
|
*/
|
|
SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag)
|
|
adr_l x1, __boot_cpu_mode
|
|
cmp w0, #BOOT_CPU_MODE_EL2
|
|
b.ne 1f
|
|
add x1, x1, #4
|
|
1: str w0, [x1] // Save CPU boot mode
|
|
dmb sy
|
|
dc ivac, x1 // Invalidate potentially stale cache line
|
|
ret
|
|
SYM_FUNC_END(set_cpu_boot_mode_flag)
|
|
|
|
/*
|
|
* These values are written with the MMU off, but read with the MMU on.
|
|
* Writers will invalidate the corresponding address, discarding up to a
|
|
* 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures
|
|
* sufficient alignment that the CWG doesn't overlap another section.
|
|
*/
|
|
.pushsection ".mmuoff.data.write", "aw"
|
|
/*
|
|
* We need to find out the CPU boot mode long after boot, so we need to
|
|
* store it in a writable variable.
|
|
*
|
|
* This is not in .bss, because we set it sufficiently early that the boot-time
|
|
* zeroing of .bss would clobber it.
|
|
*/
|
|
SYM_DATA_START(__boot_cpu_mode)
|
|
.long BOOT_CPU_MODE_EL2
|
|
.long BOOT_CPU_MODE_EL1
|
|
SYM_DATA_END(__boot_cpu_mode)
|
|
/*
|
|
* The booting CPU updates the failed status @__early_cpu_boot_status,
|
|
* with MMU turned off.
|
|
*/
|
|
SYM_DATA_START(__early_cpu_boot_status)
|
|
.quad 0
|
|
SYM_DATA_END(__early_cpu_boot_status)
|
|
|
|
.popsection
|
|
|
|
/*
|
|
* This provides a "holding pen" for platforms to hold all secondary
|
|
* cores are held until we're ready for them to initialise.
|
|
*/
|
|
SYM_FUNC_START(secondary_holding_pen)
|
|
bl init_kernel_el // w0=cpu_boot_mode
|
|
bl set_cpu_boot_mode_flag
|
|
mrs x0, mpidr_el1
|
|
mov_q x1, MPIDR_HWID_BITMASK
|
|
and x0, x0, x1
|
|
adr_l x3, secondary_holding_pen_release
|
|
pen: ldr x4, [x3]
|
|
cmp x4, x0
|
|
b.eq secondary_startup
|
|
wfe
|
|
b pen
|
|
SYM_FUNC_END(secondary_holding_pen)
|
|
|
|
/*
|
|
* Secondary entry point that jumps straight into the kernel. Only to
|
|
* be used where CPUs are brought online dynamically by the kernel.
|
|
*/
|
|
SYM_FUNC_START(secondary_entry)
|
|
bl init_kernel_el // w0=cpu_boot_mode
|
|
bl set_cpu_boot_mode_flag
|
|
b secondary_startup
|
|
SYM_FUNC_END(secondary_entry)
|
|
|
|
SYM_FUNC_START_LOCAL(secondary_startup)
|
|
/*
|
|
* Common entry point for secondary CPUs.
|
|
*/
|
|
bl switch_to_vhe
|
|
bl __cpu_secondary_check52bitva
|
|
bl __cpu_setup // initialise processor
|
|
adrp x1, swapper_pg_dir
|
|
bl __enable_mmu
|
|
ldr x8, =__secondary_switched
|
|
br x8
|
|
SYM_FUNC_END(secondary_startup)
|
|
|
|
SYM_FUNC_START_LOCAL(__secondary_switched)
|
|
adr_l x5, vectors
|
|
msr vbar_el1, x5
|
|
isb
|
|
|
|
adr_l x0, secondary_data
|
|
ldr x2, [x0, #CPU_BOOT_TASK]
|
|
cbz x2, __secondary_too_slow
|
|
|
|
init_cpu_task x2, x1, x3
|
|
|
|
#ifdef CONFIG_ARM64_PTR_AUTH
|
|
ptrauth_keys_init_cpu x2, x3, x4, x5
|
|
#endif
|
|
|
|
bl secondary_start_kernel
|
|
ASM_BUG()
|
|
SYM_FUNC_END(__secondary_switched)
|
|
|
|
SYM_FUNC_START_LOCAL(__secondary_too_slow)
|
|
wfe
|
|
wfi
|
|
b __secondary_too_slow
|
|
SYM_FUNC_END(__secondary_too_slow)
|
|
|
|
/*
|
|
* The booting CPU updates the failed status @__early_cpu_boot_status,
|
|
* with MMU turned off.
|
|
*
|
|
* update_early_cpu_boot_status tmp, status
|
|
* - Corrupts tmp1, tmp2
|
|
* - Writes 'status' to __early_cpu_boot_status and makes sure
|
|
* it is committed to memory.
|
|
*/
|
|
|
|
.macro update_early_cpu_boot_status status, tmp1, tmp2
|
|
mov \tmp2, #\status
|
|
adr_l \tmp1, __early_cpu_boot_status
|
|
str \tmp2, [\tmp1]
|
|
dmb sy
|
|
dc ivac, \tmp1 // Invalidate potentially stale cache line
|
|
.endm
|
|
|
|
/*
|
|
* Enable the MMU.
|
|
*
|
|
* x0 = SCTLR_EL1 value for turning on the MMU.
|
|
* x1 = TTBR1_EL1 value
|
|
*
|
|
* Returns to the caller via x30/lr. This requires the caller to be covered
|
|
* by the .idmap.text section.
|
|
*
|
|
* Checks if the selected granule size is supported by the CPU.
|
|
* If it isn't, park the CPU
|
|
*/
|
|
SYM_FUNC_START(__enable_mmu)
|
|
mrs x2, ID_AA64MMFR0_EL1
|
|
ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4
|
|
cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MIN
|
|
b.lt __no_granule_support
|
|
cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX
|
|
b.gt __no_granule_support
|
|
update_early_cpu_boot_status 0, x2, x3
|
|
adrp x2, idmap_pg_dir
|
|
phys_to_ttbr x1, x1
|
|
phys_to_ttbr x2, x2
|
|
msr ttbr0_el1, x2 // load TTBR0
|
|
offset_ttbr1 x1, x3
|
|
msr ttbr1_el1, x1 // load TTBR1
|
|
isb
|
|
|
|
set_sctlr_el1 x0
|
|
|
|
ret
|
|
SYM_FUNC_END(__enable_mmu)
|
|
|
|
SYM_FUNC_START(__cpu_secondary_check52bitva)
|
|
#ifdef CONFIG_ARM64_VA_BITS_52
|
|
ldr_l x0, vabits_actual
|
|
cmp x0, #52
|
|
b.ne 2f
|
|
|
|
mrs_s x0, SYS_ID_AA64MMFR2_EL1
|
|
and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
|
|
cbnz x0, 2f
|
|
|
|
update_early_cpu_boot_status \
|
|
CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1
|
|
1: wfe
|
|
wfi
|
|
b 1b
|
|
|
|
#endif
|
|
2: ret
|
|
SYM_FUNC_END(__cpu_secondary_check52bitva)
|
|
|
|
SYM_FUNC_START_LOCAL(__no_granule_support)
|
|
/* Indicate that this CPU can't boot and is stuck in the kernel */
|
|
update_early_cpu_boot_status \
|
|
CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2
|
|
1:
|
|
wfe
|
|
wfi
|
|
b 1b
|
|
SYM_FUNC_END(__no_granule_support)
|
|
|
|
#ifdef CONFIG_RELOCATABLE
|
|
SYM_FUNC_START_LOCAL(__relocate_kernel)
|
|
/*
|
|
* Iterate over each entry in the relocation table, and apply the
|
|
* relocations in place.
|
|
*/
|
|
ldr w9, =__rela_offset // offset to reloc table
|
|
ldr w10, =__rela_size // size of reloc table
|
|
|
|
mov_q x11, KIMAGE_VADDR // default virtual offset
|
|
add x11, x11, x23 // actual virtual offset
|
|
add x9, x9, x11 // __va(.rela)
|
|
add x10, x9, x10 // __va(.rela) + sizeof(.rela)
|
|
|
|
0: cmp x9, x10
|
|
b.hs 1f
|
|
ldp x12, x13, [x9], #24
|
|
ldr x14, [x9, #-8]
|
|
cmp w13, #R_AARCH64_RELATIVE
|
|
b.ne 0b
|
|
add x14, x14, x23 // relocate
|
|
str x14, [x12, x23]
|
|
b 0b
|
|
|
|
1:
|
|
#ifdef CONFIG_RELR
|
|
/*
|
|
* Apply RELR relocations.
|
|
*
|
|
* RELR is a compressed format for storing relative relocations. The
|
|
* encoded sequence of entries looks like:
|
|
* [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ]
|
|
*
|
|
* i.e. start with an address, followed by any number of bitmaps. The
|
|
* address entry encodes 1 relocation. The subsequent bitmap entries
|
|
* encode up to 63 relocations each, at subsequent offsets following
|
|
* the last address entry.
|
|
*
|
|
* The bitmap entries must have 1 in the least significant bit. The
|
|
* assumption here is that an address cannot have 1 in lsb. Odd
|
|
* addresses are not supported. Any odd addresses are stored in the RELA
|
|
* section, which is handled above.
|
|
*
|
|
* Excluding the least significant bit in the bitmap, each non-zero
|
|
* bit in the bitmap represents a relocation to be applied to
|
|
* a corresponding machine word that follows the base address
|
|
* word. The second least significant bit represents the machine
|
|
* word immediately following the initial address, and each bit
|
|
* that follows represents the next word, in linear order. As such,
|
|
* a single bitmap can encode up to 63 relocations in a 64-bit object.
|
|
*
|
|
* In this implementation we store the address of the next RELR table
|
|
* entry in x9, the address being relocated by the current address or
|
|
* bitmap entry in x13 and the address being relocated by the current
|
|
* bit in x14.
|
|
*
|
|
* Because addends are stored in place in the binary, RELR relocations
|
|
* cannot be applied idempotently. We use x24 to keep track of the
|
|
* currently applied displacement so that we can correctly relocate if
|
|
* __relocate_kernel is called twice with non-zero displacements (i.e.
|
|
* if there is both a physical misalignment and a KASLR displacement).
|
|
*/
|
|
ldr w9, =__relr_offset // offset to reloc table
|
|
ldr w10, =__relr_size // size of reloc table
|
|
add x9, x9, x11 // __va(.relr)
|
|
add x10, x9, x10 // __va(.relr) + sizeof(.relr)
|
|
|
|
sub x15, x23, x24 // delta from previous offset
|
|
cbz x15, 7f // nothing to do if unchanged
|
|
mov x24, x23 // save new offset
|
|
|
|
2: cmp x9, x10
|
|
b.hs 7f
|
|
ldr x11, [x9], #8
|
|
tbnz x11, #0, 3f // branch to handle bitmaps
|
|
add x13, x11, x23
|
|
ldr x12, [x13] // relocate address entry
|
|
add x12, x12, x15
|
|
str x12, [x13], #8 // adjust to start of bitmap
|
|
b 2b
|
|
|
|
3: mov x14, x13
|
|
4: lsr x11, x11, #1
|
|
cbz x11, 6f
|
|
tbz x11, #0, 5f // skip bit if not set
|
|
ldr x12, [x14] // relocate bit
|
|
add x12, x12, x15
|
|
str x12, [x14]
|
|
|
|
5: add x14, x14, #8 // move to next bit's address
|
|
b 4b
|
|
|
|
6: /*
|
|
* Move to the next bitmap's address. 8 is the word size, and 63 is the
|
|
* number of significant bits in a bitmap entry.
|
|
*/
|
|
add x13, x13, #(8 * 63)
|
|
b 2b
|
|
|
|
7:
|
|
#endif
|
|
ret
|
|
|
|
SYM_FUNC_END(__relocate_kernel)
|
|
#endif
|
|
|
|
SYM_FUNC_START_LOCAL(__primary_switch)
|
|
#ifdef CONFIG_RANDOMIZE_BASE
|
|
mov x19, x0 // preserve new SCTLR_EL1 value
|
|
mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value
|
|
#endif
|
|
|
|
adrp x1, init_pg_dir
|
|
bl __enable_mmu
|
|
#ifdef CONFIG_RELOCATABLE
|
|
#ifdef CONFIG_RELR
|
|
mov x24, #0 // no RELR displacement yet
|
|
#endif
|
|
bl __relocate_kernel
|
|
#ifdef CONFIG_RANDOMIZE_BASE
|
|
ldr x8, =__primary_switched
|
|
adrp x0, __PHYS_OFFSET
|
|
blr x8
|
|
|
|
/*
|
|
* If we return here, we have a KASLR displacement in x23 which we need
|
|
* to take into account by discarding the current kernel mapping and
|
|
* creating a new one.
|
|
*/
|
|
pre_disable_mmu_workaround
|
|
msr sctlr_el1, x20 // disable the MMU
|
|
isb
|
|
bl __create_page_tables // recreate kernel mapping
|
|
|
|
tlbi vmalle1 // Remove any stale TLB entries
|
|
dsb nsh
|
|
isb
|
|
|
|
set_sctlr_el1 x19 // re-enable the MMU
|
|
|
|
bl __relocate_kernel
|
|
#endif
|
|
#endif
|
|
ldr x8, =__primary_switched
|
|
adrp x0, __PHYS_OFFSET
|
|
br x8
|
|
SYM_FUNC_END(__primary_switch)
|