208 строки
8.1 KiB
C
208 строки
8.1 KiB
C
/*
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* Header file for Samsung DP (Display Port) interface driver.
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*
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* Copyright (C) 2012 Samsung Electronics Co., Ltd.
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _EXYNOS_DP_CORE_H
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#define _EXYNOS_DP_CORE_H
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struct link_train {
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int eq_loop;
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int cr_loop[4];
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u8 link_rate;
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u8 lane_count;
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u8 training_lane[4];
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enum link_training_state lt_state;
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};
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struct exynos_dp_device {
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struct device *dev;
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struct clk *clock;
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unsigned int irq;
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void __iomem *reg_base;
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struct video_info *video_info;
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struct link_train link_train;
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};
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/* exynos_dp_reg.c */
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void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
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void exynos_dp_stop_video(struct exynos_dp_device *dp);
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void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
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void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
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void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
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void exynos_dp_reset(struct exynos_dp_device *dp);
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void exynos_dp_swreset(struct exynos_dp_device *dp);
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void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
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u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
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void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
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void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
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enum analog_power_block block,
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bool enable);
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void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
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void exynos_dp_init_hpd(struct exynos_dp_device *dp);
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void exynos_dp_reset_aux(struct exynos_dp_device *dp);
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void exynos_dp_init_aux(struct exynos_dp_device *dp);
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int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
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void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
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int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
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int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
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unsigned int reg_addr,
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unsigned char data);
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int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
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unsigned int reg_addr,
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unsigned char *data);
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int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char data[]);
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int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char data[]);
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int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr);
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int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr,
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unsigned int *data);
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int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char edid[]);
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void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
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void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
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void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
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void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
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void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
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void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
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void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
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void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
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void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
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void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
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enum pattern_set pattern);
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void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
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void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
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void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
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void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
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void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
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u32 training_lane);
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void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
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u32 training_lane);
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void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
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u32 training_lane);
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void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
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u32 training_lane);
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u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
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u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
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u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
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u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
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void exynos_dp_reset_macro(struct exynos_dp_device *dp);
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int exynos_dp_init_video(struct exynos_dp_device *dp);
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void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
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u32 color_depth,
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u32 color_space,
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u32 dynamic_range,
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u32 ycbcr_coeff);
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int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
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void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
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enum clock_recovery_m_value_type type,
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u32 m_value,
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u32 n_value);
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void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
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void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
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void exynos_dp_start_video(struct exynos_dp_device *dp);
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int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
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void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
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struct video_info *video_info);
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void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
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void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
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/* I2C EDID Chip ID, Slave Address */
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#define I2C_EDID_DEVICE_ADDR 0x50
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#define I2C_E_EDID_DEVICE_ADDR 0x30
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#define EDID_BLOCK_LENGTH 0x80
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#define EDID_HEADER_PATTERN 0x00
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#define EDID_EXTENSION_FLAG 0x7e
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#define EDID_CHECKSUM 0x7f
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/* Definition for DPCD Register */
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#define DPCD_ADDR_DPCD_REV 0x0000
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#define DPCD_ADDR_MAX_LINK_RATE 0x0001
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#define DPCD_ADDR_MAX_LANE_COUNT 0x0002
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#define DPCD_ADDR_LINK_BW_SET 0x0100
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#define DPCD_ADDR_LANE_COUNT_SET 0x0101
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#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
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#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
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#define DPCD_ADDR_LANE0_1_STATUS 0x0202
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#define DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204
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#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
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#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
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#define DPCD_ADDR_TEST_REQUEST 0x0218
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#define DPCD_ADDR_TEST_RESPONSE 0x0260
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#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
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#define DPCD_ADDR_SINK_POWER_STATE 0x0600
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/* DPCD_ADDR_MAX_LANE_COUNT */
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#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
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#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
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/* DPCD_ADDR_LANE_COUNT_SET */
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#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
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#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
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/* DPCD_ADDR_TRAINING_PATTERN_SET */
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#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
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#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
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#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
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#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
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#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
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/* DPCD_ADDR_TRAINING_LANE0_SET */
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#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
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#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
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#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
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#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
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#define DPCD_MAX_SWING_REACHED (0x1 << 2)
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#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
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#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
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#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
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/* DPCD_ADDR_LANE0_1_STATUS */
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#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
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#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
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#define DPCD_LANE_CR_DONE (0x1 << 0)
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#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
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DPCD_LANE_CHANNEL_EQ_DONE|\
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DPCD_LANE_SYMBOL_LOCKED)
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/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
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#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
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#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
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#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
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/* DPCD_ADDR_TEST_REQUEST */
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#define DPCD_TEST_EDID_READ (0x1 << 2)
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/* DPCD_ADDR_TEST_RESPONSE */
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#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
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/* DPCD_ADDR_SINK_POWER_STATE */
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#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
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#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
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#endif /* _EXYNOS_DP_CORE_H */
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