494 строки
13 KiB
C
494 строки
13 KiB
C
/*
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* Broadcom SATA3 AHCI Controller PHY Driver
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*
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* Copyright (C) 2016 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#define SATA_PCB_BANK_OFFSET 0x23c
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#define SATA_PCB_REG_OFFSET(ofs) ((ofs) * 4)
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#define MAX_PORTS 2
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/* Register offset between PHYs in PCB space */
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#define SATA_PCB_REG_28NM_SPACE_SIZE 0x1000
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/* The older SATA PHY registers duplicated per port registers within the map,
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* rather than having a separate map per port.
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*/
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#define SATA_PCB_REG_40NM_SPACE_SIZE 0x10
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/* Register offset between PHYs in PHY control space */
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#define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8
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enum brcm_sata_phy_version {
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BRCM_SATA_PHY_STB_28NM,
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BRCM_SATA_PHY_STB_40NM,
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BRCM_SATA_PHY_IPROC_NS2,
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BRCM_SATA_PHY_IPROC_NSP,
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};
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struct brcm_sata_port {
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int portnum;
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struct phy *phy;
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struct brcm_sata_phy *phy_priv;
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bool ssc_en;
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};
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struct brcm_sata_phy {
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struct device *dev;
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void __iomem *phy_base;
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void __iomem *ctrl_base;
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enum brcm_sata_phy_version version;
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struct brcm_sata_port phys[MAX_PORTS];
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};
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enum sata_phy_regs {
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BLOCK0_REG_BANK = 0x000,
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BLOCK0_XGXSSTATUS = 0x81,
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BLOCK0_XGXSSTATUS_PLL_LOCK = BIT(12),
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BLOCK0_SPARE = 0x8d,
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BLOCK0_SPARE_OOB_CLK_SEL_MASK = 0x3,
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BLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 0x1,
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PLL_REG_BANK_0 = 0x050,
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PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
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PLLCONTROL_0_FREQ_DET_RESTART = BIT(13),
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PLLCONTROL_0_FREQ_MONITOR = BIT(12),
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PLLCONTROL_0_SEQ_START = BIT(15),
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PLL_CAP_CONTROL = 0x85,
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PLL_ACTRL2 = 0x8b,
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PLL_ACTRL2_SELDIV_MASK = 0x1f,
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PLL_ACTRL2_SELDIV_SHIFT = 9,
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PLL1_REG_BANK = 0x060,
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PLL1_ACTRL2 = 0x82,
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PLL1_ACTRL3 = 0x83,
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PLL1_ACTRL4 = 0x84,
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OOB_REG_BANK = 0x150,
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OOB1_REG_BANK = 0x160,
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OOB_CTRL1 = 0x80,
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OOB_CTRL1_BURST_MAX_MASK = 0xf,
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OOB_CTRL1_BURST_MAX_SHIFT = 12,
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OOB_CTRL1_BURST_MIN_MASK = 0xf,
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OOB_CTRL1_BURST_MIN_SHIFT = 8,
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OOB_CTRL1_WAKE_IDLE_MAX_MASK = 0xf,
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OOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4,
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OOB_CTRL1_WAKE_IDLE_MIN_MASK = 0xf,
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OOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0,
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OOB_CTRL2 = 0x81,
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OOB_CTRL2_SEL_ENA_SHIFT = 15,
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OOB_CTRL2_SEL_ENA_RC_SHIFT = 14,
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OOB_CTRL2_RESET_IDLE_MAX_MASK = 0x3f,
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OOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8,
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OOB_CTRL2_BURST_CNT_MASK = 0x3,
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OOB_CTRL2_BURST_CNT_SHIFT = 6,
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OOB_CTRL2_RESET_IDLE_MIN_MASK = 0x3f,
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OOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0,
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TXPMD_REG_BANK = 0x1a0,
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TXPMD_CONTROL1 = 0x81,
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TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
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TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1),
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TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
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TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
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TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
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TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
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TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
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};
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enum sata_phy_ctrl_regs {
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PHY_CTRL_1 = 0x0,
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PHY_CTRL_1_RESET = BIT(0),
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};
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static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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u32 size = 0;
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switch (priv->version) {
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case BRCM_SATA_PHY_STB_28NM:
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case BRCM_SATA_PHY_IPROC_NS2:
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size = SATA_PCB_REG_28NM_SPACE_SIZE;
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break;
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case BRCM_SATA_PHY_STB_40NM:
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size = SATA_PCB_REG_40NM_SPACE_SIZE;
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break;
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default:
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dev_err(priv->dev, "invalid phy version\n");
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break;
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}
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return priv->phy_base + (port->portnum * size);
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}
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static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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u32 size = 0;
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switch (priv->version) {
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case BRCM_SATA_PHY_IPROC_NS2:
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size = SATA_PHY_CTRL_REG_28NM_SPACE_SIZE;
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break;
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default:
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dev_err(priv->dev, "invalid phy version\n");
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break;
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}
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return priv->ctrl_base + (port->portnum * size);
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}
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static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank,
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u32 ofs, u32 msk, u32 value)
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{
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u32 tmp;
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writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
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tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
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tmp = (tmp & msk) | value;
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writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
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}
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static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
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{
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writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
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return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
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}
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/* These defaults were characterized by H/W group */
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#define STB_FMIN_VAL_DEFAULT 0x3df
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#define STB_FMAX_VAL_DEFAULT 0x3df
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#define STB_FMAX_VAL_SSC 0x83
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static int brcm_stb_sata_init(struct brcm_sata_port *port)
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{
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void __iomem *base = brcm_sata_pcb_base(port);
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struct brcm_sata_phy *priv = port->phy_priv;
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u32 tmp;
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/* override the TX spread spectrum setting */
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tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
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brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
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/* set fixed min freq */
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brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
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~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
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STB_FMIN_VAL_DEFAULT);
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/* set fixed max freq depending on SSC config */
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if (port->ssc_en) {
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dev_info(priv->dev, "enabling SSC on port%d\n", port->portnum);
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tmp = STB_FMAX_VAL_SSC;
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} else {
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tmp = STB_FMAX_VAL_DEFAULT;
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}
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brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
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~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
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return 0;
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}
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/* NS2 SATA PLL1 defaults were characterized by H/W group */
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#define NS2_PLL1_ACTRL2_MAGIC 0x1df8
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#define NS2_PLL1_ACTRL3_MAGIC 0x2b00
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#define NS2_PLL1_ACTRL4_MAGIC 0x8824
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static int brcm_ns2_sata_init(struct brcm_sata_port *port)
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{
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int try;
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unsigned int val;
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void __iomem *base = brcm_sata_pcb_base(port);
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void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
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struct device *dev = port->phy_priv->dev;
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/* Configure OOB control */
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val = 0x0;
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val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT);
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val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
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val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
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val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
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brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
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val = 0x0;
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val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
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val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
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val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
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brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
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/* Configure PHY PLL register bank 1 */
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val = NS2_PLL1_ACTRL2_MAGIC;
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
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val = NS2_PLL1_ACTRL3_MAGIC;
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
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val = NS2_PLL1_ACTRL4_MAGIC;
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
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/* Configure PHY BLOCK0 register bank */
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/* Set oob_clk_sel to refclk/2 */
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brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE,
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~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
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BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
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/* Strobe PHY reset using PHY control register */
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writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1);
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mdelay(1);
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writel(0x0, ctrl_base + PHY_CTRL_1);
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mdelay(1);
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/* Wait for PHY PLL lock by polling pll_lock bit */
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try = 50;
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while (try) {
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val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
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BLOCK0_XGXSSTATUS);
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if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
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break;
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msleep(20);
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try--;
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}
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if (!try) {
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/* PLL did not lock; give up */
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dev_err(dev, "port%d PLL did not lock\n", port->portnum);
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return -ETIMEDOUT;
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}
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dev_dbg(dev, "port%d initialized\n", port->portnum);
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return 0;
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}
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static int brcm_nsp_sata_init(struct brcm_sata_port *port)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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struct device *dev = port->phy_priv->dev;
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void __iomem *base = priv->phy_base;
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unsigned int oob_bank;
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unsigned int val, try;
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/* Configure OOB control */
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if (port->portnum == 0)
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oob_bank = OOB_REG_BANK;
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else if (port->portnum == 1)
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oob_bank = OOB1_REG_BANK;
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else
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return -EINVAL;
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val = 0x0;
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val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT);
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val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
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val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
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val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
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brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val);
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val = 0x0;
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val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
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val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
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val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
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brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val);
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brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2,
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~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
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0x0c << PLL_ACTRL2_SELDIV_SHIFT);
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brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL,
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0xff0, 0x4f0);
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val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
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brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
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~val, val);
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val = PLLCONTROL_0_SEQ_START;
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brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
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~val, 0);
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mdelay(10);
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brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
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~val, val);
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/* Wait for pll_seq_done bit */
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try = 50;
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while (try--) {
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val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
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BLOCK0_XGXSSTATUS);
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if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
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break;
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msleep(20);
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}
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if (!try) {
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/* PLL did not lock; give up */
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dev_err(dev, "port%d PLL did not lock\n", port->portnum);
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return -ETIMEDOUT;
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}
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dev_dbg(dev, "port%d initialized\n", port->portnum);
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return 0;
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}
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static int brcm_sata_phy_init(struct phy *phy)
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{
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int rc;
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struct brcm_sata_port *port = phy_get_drvdata(phy);
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switch (port->phy_priv->version) {
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case BRCM_SATA_PHY_STB_28NM:
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case BRCM_SATA_PHY_STB_40NM:
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rc = brcm_stb_sata_init(port);
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break;
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case BRCM_SATA_PHY_IPROC_NS2:
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rc = brcm_ns2_sata_init(port);
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break;
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case BRCM_SATA_PHY_IPROC_NSP:
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rc = brcm_nsp_sata_init(port);
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break;
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default:
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rc = -ENODEV;
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}
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return rc;
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}
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static const struct phy_ops phy_ops = {
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.init = brcm_sata_phy_init,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id brcm_sata_phy_of_match[] = {
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{ .compatible = "brcm,bcm7445-sata-phy",
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.data = (void *)BRCM_SATA_PHY_STB_28NM },
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{ .compatible = "brcm,bcm7425-sata-phy",
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.data = (void *)BRCM_SATA_PHY_STB_40NM },
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{ .compatible = "brcm,iproc-ns2-sata-phy",
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.data = (void *)BRCM_SATA_PHY_IPROC_NS2 },
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{ .compatible = "brcm,iproc-nsp-sata-phy",
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.data = (void *)BRCM_SATA_PHY_IPROC_NSP },
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{},
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};
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MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
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static int brcm_sata_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *dn = dev->of_node, *child;
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const struct of_device_id *of_id;
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struct brcm_sata_phy *priv;
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struct resource *res;
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struct phy_provider *provider;
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int ret, count = 0;
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if (of_get_child_count(dn) == 0)
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return -ENODEV;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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dev_set_drvdata(dev, priv);
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priv->dev = dev;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
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priv->phy_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->phy_base))
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return PTR_ERR(priv->phy_base);
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of_id = of_match_node(brcm_sata_phy_of_match, dn);
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if (of_id)
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priv->version = (enum brcm_sata_phy_version)of_id->data;
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else
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priv->version = BRCM_SATA_PHY_STB_28NM;
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if (priv->version == BRCM_SATA_PHY_IPROC_NS2) {
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"phy-ctrl");
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priv->ctrl_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->ctrl_base))
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return PTR_ERR(priv->ctrl_base);
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}
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for_each_available_child_of_node(dn, child) {
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unsigned int id;
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struct brcm_sata_port *port;
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if (of_property_read_u32(child, "reg", &id)) {
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dev_err(dev, "missing reg property in node %s\n",
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child->name);
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ret = -EINVAL;
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goto put_child;
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}
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if (id >= MAX_PORTS) {
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dev_err(dev, "invalid reg: %u\n", id);
|
|
ret = -EINVAL;
|
|
goto put_child;
|
|
}
|
|
if (priv->phys[id].phy) {
|
|
dev_err(dev, "already registered port %u\n", id);
|
|
ret = -EINVAL;
|
|
goto put_child;
|
|
}
|
|
|
|
port = &priv->phys[id];
|
|
port->portnum = id;
|
|
port->phy_priv = priv;
|
|
port->phy = devm_phy_create(dev, child, &phy_ops);
|
|
port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
|
|
if (IS_ERR(port->phy)) {
|
|
dev_err(dev, "failed to create PHY\n");
|
|
ret = PTR_ERR(port->phy);
|
|
goto put_child;
|
|
}
|
|
|
|
phy_set_drvdata(port->phy, port);
|
|
count++;
|
|
}
|
|
|
|
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
if (IS_ERR(provider)) {
|
|
dev_err(dev, "could not register PHY provider\n");
|
|
return PTR_ERR(provider);
|
|
}
|
|
|
|
dev_info(dev, "registered %d port(s)\n", count);
|
|
|
|
return 0;
|
|
put_child:
|
|
of_node_put(child);
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver brcm_sata_phy_driver = {
|
|
.probe = brcm_sata_phy_probe,
|
|
.driver = {
|
|
.of_match_table = brcm_sata_phy_of_match,
|
|
.name = "brcm-sata-phy",
|
|
}
|
|
};
|
|
module_platform_driver(brcm_sata_phy_driver);
|
|
|
|
MODULE_DESCRIPTION("Broadcom SATA PHY driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Marc Carino");
|
|
MODULE_AUTHOR("Brian Norris");
|
|
MODULE_ALIAS("platform:phy-brcm-sata");
|