440 строки
10 KiB
C
440 строки
10 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <lantiq_soc.h>
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#define DRV_NAME "sflash-falcon"
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#define FALCON_SPI_XFER_BEGIN (1 << 0)
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#define FALCON_SPI_XFER_END (1 << 1)
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/* Bus Read Configuration Register0 */
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#define BUSRCON0 0x00000010
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/* Bus Write Configuration Register0 */
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#define BUSWCON0 0x00000018
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/* Serial Flash Configuration Register */
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#define SFCON 0x00000080
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/* Serial Flash Time Register */
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#define SFTIME 0x00000084
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/* Serial Flash Status Register */
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#define SFSTAT 0x00000088
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/* Serial Flash Command Register */
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#define SFCMD 0x0000008C
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/* Serial Flash Address Register */
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#define SFADDR 0x00000090
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/* Serial Flash Data Register */
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#define SFDATA 0x00000094
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/* Serial Flash I/O Control Register */
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#define SFIO 0x00000098
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/* EBU Clock Control Register */
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#define EBUCC 0x000000C4
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/* Dummy Phase Length */
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#define SFCMD_DUMLEN_OFFSET 16
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#define SFCMD_DUMLEN_MASK 0x000F0000
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/* Chip Select */
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#define SFCMD_CS_OFFSET 24
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#define SFCMD_CS_MASK 0x07000000
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/* field offset */
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#define SFCMD_ALEN_OFFSET 20
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#define SFCMD_ALEN_MASK 0x00700000
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/* SCK Rise-edge Position */
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#define SFTIME_SCKR_POS_OFFSET 8
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#define SFTIME_SCKR_POS_MASK 0x00000F00
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/* SCK Period */
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#define SFTIME_SCK_PER_OFFSET 0
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#define SFTIME_SCK_PER_MASK 0x0000000F
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/* SCK Fall-edge Position */
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#define SFTIME_SCKF_POS_OFFSET 12
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#define SFTIME_SCKF_POS_MASK 0x0000F000
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/* Device Size */
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#define SFCON_DEV_SIZE_A23_0 0x03000000
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#define SFCON_DEV_SIZE_MASK 0x0F000000
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/* Read Data Position */
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#define SFTIME_RD_POS_MASK 0x000F0000
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/* Data Output */
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#define SFIO_UNUSED_WD_MASK 0x0000000F
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/* Command Opcode mask */
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#define SFCMD_OPC_MASK 0x000000FF
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/* dlen bytes of data to write */
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#define SFCMD_DIR_WRITE 0x00000100
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/* Data Length offset */
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#define SFCMD_DLEN_OFFSET 9
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/* Command Error */
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#define SFSTAT_CMD_ERR 0x20000000
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/* Access Command Pending */
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#define SFSTAT_CMD_PEND 0x00400000
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/* Frequency set to 100MHz. */
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#define EBUCC_EBUDIV_SELF100 0x00000001
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/* Serial Flash */
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#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
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/* 8-bit multiplexed */
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#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
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/* Serial Flash */
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#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
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/* Chip Select after opcode */
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#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
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#define CLOCK_100M 100000000
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#define CLOCK_50M 50000000
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struct falcon_sflash {
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u32 sfcmd; /* for caching of opcode, direction, ... */
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struct spi_master *master;
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};
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int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
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unsigned long flags)
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{
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struct device *dev = &spi->dev;
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struct falcon_sflash *priv = spi_master_get_devdata(spi->master);
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const u8 *txp = t->tx_buf;
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u8 *rxp = t->rx_buf;
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unsigned int bytelen = ((8 * t->len + 7) / 8);
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unsigned int len, alen, dumlen;
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u32 val;
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enum {
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state_init,
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state_command_prepare,
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state_write,
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state_read,
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state_disable_cs,
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state_end
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} state = state_init;
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do {
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switch (state) {
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case state_init: /* detect phase of upper layer sequence */
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{
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/* initial write ? */
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if (flags & FALCON_SPI_XFER_BEGIN) {
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if (!txp) {
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dev_err(dev,
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"BEGIN without tx data!\n");
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return -ENODATA;
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}
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/*
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* Prepare the parts of the sfcmd register,
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* which should not change during a sequence!
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* Only exception are the length fields,
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* especially alen and dumlen.
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*/
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priv->sfcmd = ((spi->chip_select
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<< SFCMD_CS_OFFSET)
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& SFCMD_CS_MASK);
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priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
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priv->sfcmd |= *txp;
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txp++;
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bytelen--;
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if (bytelen) {
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/*
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* more data:
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* maybe address and/or dummy
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*/
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state = state_command_prepare;
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break;
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} else {
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dev_dbg(dev, "write cmd %02X\n",
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priv->sfcmd & SFCMD_OPC_MASK);
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}
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}
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/* continued write ? */
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if (txp && bytelen) {
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state = state_write;
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break;
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}
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/* read data? */
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if (rxp && bytelen) {
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state = state_read;
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break;
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}
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/* end of sequence? */
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if (flags & FALCON_SPI_XFER_END)
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state = state_disable_cs;
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else
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state = state_end;
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break;
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}
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/* collect tx data for address and dummy phase */
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case state_command_prepare:
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{
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/* txp is valid, already checked */
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val = 0;
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alen = 0;
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dumlen = 0;
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while (bytelen > 0) {
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if (alen < 3) {
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val = (val << 8) | (*txp++);
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alen++;
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} else if ((dumlen < 15) && (*txp == 0)) {
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/*
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* assume dummy bytes are set to 0
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* from upper layer
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*/
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dumlen++;
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txp++;
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} else {
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break;
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}
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bytelen--;
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}
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priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
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priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
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(dumlen << SFCMD_DUMLEN_OFFSET);
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if (alen > 0)
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ltq_ebu_w32(val, SFADDR);
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dev_dbg(dev, "wr %02X, alen=%d (addr=%06X) dlen=%d\n",
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priv->sfcmd & SFCMD_OPC_MASK,
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alen, val, dumlen);
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if (bytelen > 0) {
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/* continue with write */
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state = state_write;
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} else if (flags & FALCON_SPI_XFER_END) {
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/* end of sequence? */
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state = state_disable_cs;
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} else {
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/*
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* go to end and expect another
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* call (read or write)
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*/
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state = state_end;
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}
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break;
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}
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case state_write:
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{
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/* txp still valid */
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priv->sfcmd |= SFCMD_DIR_WRITE;
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len = 0;
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val = 0;
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do {
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if (bytelen--)
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val |= (*txp++) << (8 * len++);
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if ((flags & FALCON_SPI_XFER_END)
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&& (bytelen == 0)) {
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priv->sfcmd &=
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~SFCMD_KEEP_CS_KEEP_SELECTED;
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}
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if ((len == 4) || (bytelen == 0)) {
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ltq_ebu_w32(val, SFDATA);
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ltq_ebu_w32(priv->sfcmd
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| (len<<SFCMD_DLEN_OFFSET),
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SFCMD);
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len = 0;
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val = 0;
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priv->sfcmd &= ~(SFCMD_ALEN_MASK
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| SFCMD_DUMLEN_MASK);
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}
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} while (bytelen);
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state = state_end;
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break;
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}
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case state_read:
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{
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/* read data */
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priv->sfcmd &= ~SFCMD_DIR_WRITE;
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do {
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if ((flags & FALCON_SPI_XFER_END)
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&& (bytelen <= 4)) {
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priv->sfcmd &=
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~SFCMD_KEEP_CS_KEEP_SELECTED;
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}
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len = (bytelen > 4) ? 4 : bytelen;
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bytelen -= len;
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ltq_ebu_w32(priv->sfcmd
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| (len << SFCMD_DLEN_OFFSET), SFCMD);
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priv->sfcmd &= ~(SFCMD_ALEN_MASK
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| SFCMD_DUMLEN_MASK);
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do {
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val = ltq_ebu_r32(SFSTAT);
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if (val & SFSTAT_CMD_ERR) {
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/* reset error status */
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dev_err(dev, "SFSTAT: CMD_ERR");
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dev_err(dev, " (%x)\n", val);
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ltq_ebu_w32(SFSTAT_CMD_ERR,
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SFSTAT);
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return -EBADE;
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}
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} while (val & SFSTAT_CMD_PEND);
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val = ltq_ebu_r32(SFDATA);
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do {
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*rxp = (val & 0xFF);
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rxp++;
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val >>= 8;
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len--;
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} while (len);
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} while (bytelen);
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state = state_end;
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break;
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}
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case state_disable_cs:
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{
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priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
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ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),
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SFCMD);
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val = ltq_ebu_r32(SFSTAT);
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if (val & SFSTAT_CMD_ERR) {
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/* reset error status */
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dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
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ltq_ebu_w32(SFSTAT_CMD_ERR, SFSTAT);
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return -EBADE;
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}
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state = state_end;
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break;
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}
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case state_end:
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break;
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}
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} while (state != state_end);
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return 0;
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}
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static int falcon_sflash_setup(struct spi_device *spi)
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{
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unsigned int i;
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unsigned long flags;
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spin_lock_irqsave(&ebu_lock, flags);
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if (spi->max_speed_hz >= CLOCK_100M) {
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/* set EBU clock to 100 MHz */
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ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, EBUCC);
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i = 1; /* divider */
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} else {
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/* set EBU clock to 50 MHz */
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ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, EBUCC);
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/* search for suitable divider */
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for (i = 1; i < 7; i++) {
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if (CLOCK_50M / i <= spi->max_speed_hz)
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break;
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}
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}
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/* setup period of serial clock */
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ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
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| SFTIME_SCKR_POS_MASK
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| SFTIME_SCK_PER_MASK,
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(i << SFTIME_SCKR_POS_OFFSET)
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| (i << (SFTIME_SCK_PER_OFFSET + 1)),
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SFTIME);
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/*
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* set some bits of unused_wd, to not trigger HOLD/WP
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* signals on non QUAD flashes
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*/
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ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), SFIO);
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ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
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BUSRCON0);
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ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, BUSWCON0);
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/* set address wrap around to maximum for 24-bit addresses */
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ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, SFCON);
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spin_unlock_irqrestore(&ebu_lock, flags);
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return 0;
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}
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static int falcon_sflash_xfer_one(struct spi_master *master,
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struct spi_message *m)
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{
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struct falcon_sflash *priv = spi_master_get_devdata(master);
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struct spi_transfer *t;
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unsigned long spi_flags;
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unsigned long flags;
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int ret = 0;
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priv->sfcmd = 0;
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m->actual_length = 0;
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spi_flags = FALCON_SPI_XFER_BEGIN;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (list_is_last(&t->transfer_list, &m->transfers))
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spi_flags |= FALCON_SPI_XFER_END;
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spin_lock_irqsave(&ebu_lock, flags);
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ret = falcon_sflash_xfer(m->spi, t, spi_flags);
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spin_unlock_irqrestore(&ebu_lock, flags);
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if (ret)
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break;
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m->actual_length += t->len;
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WARN_ON(t->delay_usecs || t->cs_change);
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spi_flags = 0;
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}
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m->status = ret;
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spi_finalize_current_message(master);
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return 0;
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}
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static int falcon_sflash_probe(struct platform_device *pdev)
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{
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struct falcon_sflash *priv;
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struct spi_master *master;
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int ret;
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if (ltq_boot_select() != BS_SPI) {
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dev_err(&pdev->dev, "invalid bootstrap options\n");
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return -ENODEV;
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}
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master = spi_alloc_master(&pdev->dev, sizeof(*priv));
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if (!master)
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return -ENOMEM;
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priv = spi_master_get_devdata(master);
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priv->master = master;
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master->mode_bits = SPI_MODE_3;
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master->flags = SPI_MASTER_HALF_DUPLEX;
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master->setup = falcon_sflash_setup;
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master->transfer_one_message = falcon_sflash_xfer_one;
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master->dev.of_node = pdev->dev.of_node;
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret)
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spi_master_put(master);
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return ret;
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}
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static const struct of_device_id falcon_sflash_match[] = {
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{ .compatible = "lantiq,sflash-falcon" },
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{},
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};
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MODULE_DEVICE_TABLE(of, falcon_sflash_match);
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static struct platform_driver falcon_sflash_driver = {
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.probe = falcon_sflash_probe,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = falcon_sflash_match,
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}
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};
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module_platform_driver(falcon_sflash_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Lantiq Falcon SPI/SFLASH controller driver");
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