765 строки
18 KiB
C
765 строки
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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*
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* Bluetooth support for Intel devices
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*
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* Copyright (C) 2015 Intel Corporation
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*/
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#include <linux/module.h>
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#include <linux/firmware.h>
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#include <linux/regmap.h>
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#include <asm/unaligned.h>
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#include <net/bluetooth/bluetooth.h>
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#include <net/bluetooth/hci_core.h>
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#include "btintel.h"
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#define VERSION "0.1"
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#define BDADDR_INTEL (&(bdaddr_t) {{0x00, 0x8b, 0x9e, 0x19, 0x03, 0x00}})
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int btintel_check_bdaddr(struct hci_dev *hdev)
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{
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struct hci_rp_read_bd_addr *bda;
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struct sk_buff *skb;
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skb = __hci_cmd_sync(hdev, HCI_OP_READ_BD_ADDR, 0, NULL,
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HCI_INIT_TIMEOUT);
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if (IS_ERR(skb)) {
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int err = PTR_ERR(skb);
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bt_dev_err(hdev, "Reading Intel device address failed (%d)",
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err);
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return err;
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}
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if (skb->len != sizeof(*bda)) {
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bt_dev_err(hdev, "Intel device address length mismatch");
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kfree_skb(skb);
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return -EIO;
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}
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bda = (struct hci_rp_read_bd_addr *)skb->data;
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/* For some Intel based controllers, the default Bluetooth device
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* address 00:03:19:9E:8B:00 can be found. These controllers are
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* fully operational, but have the danger of duplicate addresses
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* and that in turn can cause problems with Bluetooth operation.
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*/
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if (!bacmp(&bda->bdaddr, BDADDR_INTEL)) {
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bt_dev_err(hdev, "Found Intel default device address (%pMR)",
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&bda->bdaddr);
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set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks);
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}
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kfree_skb(skb);
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return 0;
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}
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EXPORT_SYMBOL_GPL(btintel_check_bdaddr);
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int btintel_enter_mfg(struct hci_dev *hdev)
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{
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static const u8 param[] = { 0x01, 0x00 };
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struct sk_buff *skb;
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skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT);
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if (IS_ERR(skb)) {
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bt_dev_err(hdev, "Entering manufacturer mode failed (%ld)",
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PTR_ERR(skb));
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return PTR_ERR(skb);
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}
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kfree_skb(skb);
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return 0;
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}
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EXPORT_SYMBOL_GPL(btintel_enter_mfg);
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int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched)
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{
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u8 param[] = { 0x00, 0x00 };
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struct sk_buff *skb;
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/* The 2nd command parameter specifies the manufacturing exit method:
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* 0x00: Just disable the manufacturing mode (0x00).
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* 0x01: Disable manufacturing mode and reset with patches deactivated.
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* 0x02: Disable manufacturing mode and reset with patches activated.
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*/
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if (reset)
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param[1] |= patched ? 0x02 : 0x01;
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skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT);
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if (IS_ERR(skb)) {
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bt_dev_err(hdev, "Exiting manufacturer mode failed (%ld)",
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PTR_ERR(skb));
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return PTR_ERR(skb);
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}
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kfree_skb(skb);
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return 0;
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}
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EXPORT_SYMBOL_GPL(btintel_exit_mfg);
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int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
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{
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struct sk_buff *skb;
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int err;
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skb = __hci_cmd_sync(hdev, 0xfc31, 6, bdaddr, HCI_INIT_TIMEOUT);
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if (IS_ERR(skb)) {
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err = PTR_ERR(skb);
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bt_dev_err(hdev, "Changing Intel device address failed (%d)",
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err);
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return err;
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}
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kfree_skb(skb);
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return 0;
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}
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EXPORT_SYMBOL_GPL(btintel_set_bdaddr);
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int btintel_set_diag(struct hci_dev *hdev, bool enable)
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{
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struct sk_buff *skb;
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u8 param[3];
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int err;
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if (enable) {
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param[0] = 0x03;
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param[1] = 0x03;
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param[2] = 0x03;
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} else {
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param[0] = 0x00;
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param[1] = 0x00;
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param[2] = 0x00;
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}
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skb = __hci_cmd_sync(hdev, 0xfc43, 3, param, HCI_INIT_TIMEOUT);
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if (IS_ERR(skb)) {
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err = PTR_ERR(skb);
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if (err == -ENODATA)
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goto done;
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bt_dev_err(hdev, "Changing Intel diagnostic mode failed (%d)",
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err);
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return err;
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}
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kfree_skb(skb);
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done:
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btintel_set_event_mask(hdev, enable);
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return 0;
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}
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EXPORT_SYMBOL_GPL(btintel_set_diag);
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int btintel_set_diag_mfg(struct hci_dev *hdev, bool enable)
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{
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int err, ret;
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err = btintel_enter_mfg(hdev);
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if (err)
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return err;
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ret = btintel_set_diag(hdev, enable);
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err = btintel_exit_mfg(hdev, false, false);
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if (err)
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return err;
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return ret;
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}
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EXPORT_SYMBOL_GPL(btintel_set_diag_mfg);
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void btintel_hw_error(struct hci_dev *hdev, u8 code)
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{
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struct sk_buff *skb;
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u8 type = 0x00;
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bt_dev_err(hdev, "Hardware error 0x%2.2x", code);
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skb = __hci_cmd_sync(hdev, HCI_OP_RESET, 0, NULL, HCI_INIT_TIMEOUT);
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if (IS_ERR(skb)) {
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bt_dev_err(hdev, "Reset after hardware error failed (%ld)",
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PTR_ERR(skb));
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return;
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}
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kfree_skb(skb);
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skb = __hci_cmd_sync(hdev, 0xfc22, 1, &type, HCI_INIT_TIMEOUT);
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if (IS_ERR(skb)) {
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bt_dev_err(hdev, "Retrieving Intel exception info failed (%ld)",
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PTR_ERR(skb));
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return;
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}
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if (skb->len != 13) {
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bt_dev_err(hdev, "Exception info size mismatch");
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kfree_skb(skb);
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return;
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}
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bt_dev_err(hdev, "Exception info %s", (char *)(skb->data + 1));
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kfree_skb(skb);
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}
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EXPORT_SYMBOL_GPL(btintel_hw_error);
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void btintel_version_info(struct hci_dev *hdev, struct intel_version *ver)
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{
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const char *variant;
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switch (ver->fw_variant) {
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case 0x06:
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variant = "Bootloader";
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break;
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case 0x23:
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variant = "Firmware";
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break;
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default:
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return;
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}
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bt_dev_info(hdev, "%s revision %u.%u build %u week %u %u",
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variant, ver->fw_revision >> 4, ver->fw_revision & 0x0f,
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ver->fw_build_num, ver->fw_build_ww,
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2000 + ver->fw_build_yy);
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}
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EXPORT_SYMBOL_GPL(btintel_version_info);
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int btintel_secure_send(struct hci_dev *hdev, u8 fragment_type, u32 plen,
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const void *param)
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{
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while (plen > 0) {
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struct sk_buff *skb;
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u8 cmd_param[253], fragment_len = (plen > 252) ? 252 : plen;
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cmd_param[0] = fragment_type;
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memcpy(cmd_param + 1, param, fragment_len);
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skb = __hci_cmd_sync(hdev, 0xfc09, fragment_len + 1,
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cmd_param, HCI_INIT_TIMEOUT);
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if (IS_ERR(skb))
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return PTR_ERR(skb);
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kfree_skb(skb);
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plen -= fragment_len;
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param += fragment_len;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(btintel_secure_send);
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int btintel_load_ddc_config(struct hci_dev *hdev, const char *ddc_name)
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{
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const struct firmware *fw;
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struct sk_buff *skb;
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const u8 *fw_ptr;
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int err;
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err = request_firmware_direct(&fw, ddc_name, &hdev->dev);
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if (err < 0) {
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bt_dev_err(hdev, "Failed to load Intel DDC file %s (%d)",
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ddc_name, err);
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return err;
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}
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bt_dev_info(hdev, "Found Intel DDC parameters: %s", ddc_name);
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fw_ptr = fw->data;
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/* DDC file contains one or more DDC structure which has
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* Length (1 byte), DDC ID (2 bytes), and DDC value (Length - 2).
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*/
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while (fw->size > fw_ptr - fw->data) {
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u8 cmd_plen = fw_ptr[0] + sizeof(u8);
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skb = __hci_cmd_sync(hdev, 0xfc8b, cmd_plen, fw_ptr,
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HCI_INIT_TIMEOUT);
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if (IS_ERR(skb)) {
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bt_dev_err(hdev, "Failed to send Intel_Write_DDC (%ld)",
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PTR_ERR(skb));
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release_firmware(fw);
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return PTR_ERR(skb);
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}
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fw_ptr += cmd_plen;
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kfree_skb(skb);
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}
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release_firmware(fw);
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bt_dev_info(hdev, "Applying Intel DDC parameters completed");
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return 0;
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}
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EXPORT_SYMBOL_GPL(btintel_load_ddc_config);
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int btintel_set_event_mask(struct hci_dev *hdev, bool debug)
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{
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u8 mask[8] = { 0x87, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
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struct sk_buff *skb;
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int err;
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if (debug)
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mask[1] |= 0x62;
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skb = __hci_cmd_sync(hdev, 0xfc52, 8, mask, HCI_INIT_TIMEOUT);
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if (IS_ERR(skb)) {
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err = PTR_ERR(skb);
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bt_dev_err(hdev, "Setting Intel event mask failed (%d)", err);
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return err;
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}
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kfree_skb(skb);
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return 0;
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}
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EXPORT_SYMBOL_GPL(btintel_set_event_mask);
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int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug)
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{
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int err, ret;
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err = btintel_enter_mfg(hdev);
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if (err)
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return err;
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ret = btintel_set_event_mask(hdev, debug);
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err = btintel_exit_mfg(hdev, false, false);
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if (err)
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return err;
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return ret;
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}
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EXPORT_SYMBOL_GPL(btintel_set_event_mask_mfg);
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int btintel_read_version(struct hci_dev *hdev, struct intel_version *ver)
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{
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struct sk_buff *skb;
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skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_CMD_TIMEOUT);
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if (IS_ERR(skb)) {
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bt_dev_err(hdev, "Reading Intel version information failed (%ld)",
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PTR_ERR(skb));
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return PTR_ERR(skb);
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}
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if (skb->len != sizeof(*ver)) {
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bt_dev_err(hdev, "Intel version event size mismatch");
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kfree_skb(skb);
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return -EILSEQ;
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}
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memcpy(ver, skb->data, sizeof(*ver));
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kfree_skb(skb);
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return 0;
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}
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EXPORT_SYMBOL_GPL(btintel_read_version);
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/* ------- REGMAP IBT SUPPORT ------- */
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#define IBT_REG_MODE_8BIT 0x00
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#define IBT_REG_MODE_16BIT 0x01
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#define IBT_REG_MODE_32BIT 0x02
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struct regmap_ibt_context {
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struct hci_dev *hdev;
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__u16 op_write;
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__u16 op_read;
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};
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struct ibt_cp_reg_access {
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__le32 addr;
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__u8 mode;
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__u8 len;
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__u8 data[];
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} __packed;
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struct ibt_rp_reg_access {
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__u8 status;
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__le32 addr;
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__u8 data[];
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} __packed;
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static int regmap_ibt_read(void *context, const void *addr, size_t reg_size,
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void *val, size_t val_size)
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{
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struct regmap_ibt_context *ctx = context;
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struct ibt_cp_reg_access cp;
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struct ibt_rp_reg_access *rp;
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struct sk_buff *skb;
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int err = 0;
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if (reg_size != sizeof(__le32))
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return -EINVAL;
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switch (val_size) {
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case 1:
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cp.mode = IBT_REG_MODE_8BIT;
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break;
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case 2:
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cp.mode = IBT_REG_MODE_16BIT;
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break;
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case 4:
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cp.mode = IBT_REG_MODE_32BIT;
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break;
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default:
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return -EINVAL;
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}
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/* regmap provides a little-endian formatted addr */
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cp.addr = *(__le32 *)addr;
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cp.len = val_size;
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bt_dev_dbg(ctx->hdev, "Register (0x%x) read", le32_to_cpu(cp.addr));
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skb = hci_cmd_sync(ctx->hdev, ctx->op_read, sizeof(cp), &cp,
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HCI_CMD_TIMEOUT);
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if (IS_ERR(skb)) {
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err = PTR_ERR(skb);
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bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error (%d)",
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le32_to_cpu(cp.addr), err);
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return err;
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}
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if (skb->len != sizeof(*rp) + val_size) {
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bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad len",
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le32_to_cpu(cp.addr));
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err = -EINVAL;
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goto done;
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}
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rp = (struct ibt_rp_reg_access *)skb->data;
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if (rp->addr != cp.addr) {
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bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad addr",
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le32_to_cpu(rp->addr));
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err = -EINVAL;
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goto done;
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}
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memcpy(val, rp->data, val_size);
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done:
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kfree_skb(skb);
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return err;
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}
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static int regmap_ibt_gather_write(void *context,
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const void *addr, size_t reg_size,
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const void *val, size_t val_size)
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{
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struct regmap_ibt_context *ctx = context;
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struct ibt_cp_reg_access *cp;
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struct sk_buff *skb;
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int plen = sizeof(*cp) + val_size;
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u8 mode;
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int err = 0;
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if (reg_size != sizeof(__le32))
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return -EINVAL;
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switch (val_size) {
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case 1:
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mode = IBT_REG_MODE_8BIT;
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break;
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case 2:
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mode = IBT_REG_MODE_16BIT;
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break;
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case 4:
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mode = IBT_REG_MODE_32BIT;
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break;
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default:
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return -EINVAL;
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}
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cp = kmalloc(plen, GFP_KERNEL);
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if (!cp)
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return -ENOMEM;
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/* regmap provides a little-endian formatted addr/value */
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cp->addr = *(__le32 *)addr;
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cp->mode = mode;
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cp->len = val_size;
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memcpy(&cp->data, val, val_size);
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bt_dev_dbg(ctx->hdev, "Register (0x%x) write", le32_to_cpu(cp->addr));
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skb = hci_cmd_sync(ctx->hdev, ctx->op_write, plen, cp, HCI_CMD_TIMEOUT);
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if (IS_ERR(skb)) {
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err = PTR_ERR(skb);
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bt_dev_err(ctx->hdev, "regmap: Register (0x%x) write error (%d)",
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le32_to_cpu(cp->addr), err);
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goto done;
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}
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kfree_skb(skb);
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done:
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kfree(cp);
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return err;
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}
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static int regmap_ibt_write(void *context, const void *data, size_t count)
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{
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/* data contains register+value, since we only support 32bit addr,
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* minimum data size is 4 bytes.
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*/
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if (WARN_ONCE(count < 4, "Invalid register access"))
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return -EINVAL;
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return regmap_ibt_gather_write(context, data, 4, data + 4, count - 4);
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}
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static void regmap_ibt_free_context(void *context)
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{
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kfree(context);
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}
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static struct regmap_bus regmap_ibt = {
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.read = regmap_ibt_read,
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.write = regmap_ibt_write,
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.gather_write = regmap_ibt_gather_write,
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.free_context = regmap_ibt_free_context,
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.reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
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.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
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};
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/* Config is the same for all register regions */
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static const struct regmap_config regmap_ibt_cfg = {
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|
.name = "btintel_regmap",
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
};
|
|
|
|
struct regmap *btintel_regmap_init(struct hci_dev *hdev, u16 opcode_read,
|
|
u16 opcode_write)
|
|
{
|
|
struct regmap_ibt_context *ctx;
|
|
|
|
bt_dev_info(hdev, "regmap: Init R%x-W%x region", opcode_read,
|
|
opcode_write);
|
|
|
|
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
|
|
if (!ctx)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
ctx->op_read = opcode_read;
|
|
ctx->op_write = opcode_write;
|
|
ctx->hdev = hdev;
|
|
|
|
return regmap_init(&hdev->dev, ®map_ibt, ctx, ®map_ibt_cfg);
|
|
}
|
|
EXPORT_SYMBOL_GPL(btintel_regmap_init);
|
|
|
|
int btintel_send_intel_reset(struct hci_dev *hdev, u32 boot_param)
|
|
{
|
|
struct intel_reset params = { 0x00, 0x01, 0x00, 0x01, 0x00000000 };
|
|
struct sk_buff *skb;
|
|
|
|
params.boot_param = cpu_to_le32(boot_param);
|
|
|
|
skb = __hci_cmd_sync(hdev, 0xfc01, sizeof(params), ¶ms,
|
|
HCI_INIT_TIMEOUT);
|
|
if (IS_ERR(skb)) {
|
|
bt_dev_err(hdev, "Failed to send Intel Reset command");
|
|
return PTR_ERR(skb);
|
|
}
|
|
|
|
kfree_skb(skb);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(btintel_send_intel_reset);
|
|
|
|
int btintel_read_boot_params(struct hci_dev *hdev,
|
|
struct intel_boot_params *params)
|
|
{
|
|
struct sk_buff *skb;
|
|
|
|
skb = __hci_cmd_sync(hdev, 0xfc0d, 0, NULL, HCI_INIT_TIMEOUT);
|
|
if (IS_ERR(skb)) {
|
|
bt_dev_err(hdev, "Reading Intel boot parameters failed (%ld)",
|
|
PTR_ERR(skb));
|
|
return PTR_ERR(skb);
|
|
}
|
|
|
|
if (skb->len != sizeof(*params)) {
|
|
bt_dev_err(hdev, "Intel boot parameters size mismatch");
|
|
kfree_skb(skb);
|
|
return -EILSEQ;
|
|
}
|
|
|
|
memcpy(params, skb->data, sizeof(*params));
|
|
|
|
kfree_skb(skb);
|
|
|
|
if (params->status) {
|
|
bt_dev_err(hdev, "Intel boot parameters command failed (%02x)",
|
|
params->status);
|
|
return -bt_to_errno(params->status);
|
|
}
|
|
|
|
bt_dev_info(hdev, "Device revision is %u",
|
|
le16_to_cpu(params->dev_revid));
|
|
|
|
bt_dev_info(hdev, "Secure boot is %s",
|
|
params->secure_boot ? "enabled" : "disabled");
|
|
|
|
bt_dev_info(hdev, "OTP lock is %s",
|
|
params->otp_lock ? "enabled" : "disabled");
|
|
|
|
bt_dev_info(hdev, "API lock is %s",
|
|
params->api_lock ? "enabled" : "disabled");
|
|
|
|
bt_dev_info(hdev, "Debug lock is %s",
|
|
params->debug_lock ? "enabled" : "disabled");
|
|
|
|
bt_dev_info(hdev, "Minimum firmware build %u week %u %u",
|
|
params->min_fw_build_nn, params->min_fw_build_cw,
|
|
2000 + params->min_fw_build_yy);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(btintel_read_boot_params);
|
|
|
|
int btintel_download_firmware(struct hci_dev *hdev, const struct firmware *fw,
|
|
u32 *boot_param)
|
|
{
|
|
int err;
|
|
const u8 *fw_ptr;
|
|
u32 frag_len;
|
|
|
|
/* Start the firmware download transaction with the Init fragment
|
|
* represented by the 128 bytes of CSS header.
|
|
*/
|
|
err = btintel_secure_send(hdev, 0x00, 128, fw->data);
|
|
if (err < 0) {
|
|
bt_dev_err(hdev, "Failed to send firmware header (%d)", err);
|
|
goto done;
|
|
}
|
|
|
|
/* Send the 256 bytes of public key information from the firmware
|
|
* as the PKey fragment.
|
|
*/
|
|
err = btintel_secure_send(hdev, 0x03, 256, fw->data + 128);
|
|
if (err < 0) {
|
|
bt_dev_err(hdev, "Failed to send firmware pkey (%d)", err);
|
|
goto done;
|
|
}
|
|
|
|
/* Send the 256 bytes of signature information from the firmware
|
|
* as the Sign fragment.
|
|
*/
|
|
err = btintel_secure_send(hdev, 0x02, 256, fw->data + 388);
|
|
if (err < 0) {
|
|
bt_dev_err(hdev, "Failed to send firmware signature (%d)", err);
|
|
goto done;
|
|
}
|
|
|
|
fw_ptr = fw->data + 644;
|
|
frag_len = 0;
|
|
|
|
while (fw_ptr - fw->data < fw->size) {
|
|
struct hci_command_hdr *cmd = (void *)(fw_ptr + frag_len);
|
|
|
|
/* Each SKU has a different reset parameter to use in the
|
|
* HCI_Intel_Reset command and it is embedded in the firmware
|
|
* data. So, instead of using static value per SKU, check
|
|
* the firmware data and save it for later use.
|
|
*/
|
|
if (le16_to_cpu(cmd->opcode) == 0xfc0e) {
|
|
/* The boot parameter is the first 32-bit value
|
|
* and rest of 3 octets are reserved.
|
|
*/
|
|
*boot_param = get_unaligned_le32(fw_ptr + sizeof(*cmd));
|
|
|
|
bt_dev_dbg(hdev, "boot_param=0x%x", *boot_param);
|
|
}
|
|
|
|
frag_len += sizeof(*cmd) + cmd->plen;
|
|
|
|
/* The parameter length of the secure send command requires
|
|
* a 4 byte alignment. It happens so that the firmware file
|
|
* contains proper Intel_NOP commands to align the fragments
|
|
* as needed.
|
|
*
|
|
* Send set of commands with 4 byte alignment from the
|
|
* firmware data buffer as a single Data fragement.
|
|
*/
|
|
if (!(frag_len % 4)) {
|
|
err = btintel_secure_send(hdev, 0x01, frag_len, fw_ptr);
|
|
if (err < 0) {
|
|
bt_dev_err(hdev,
|
|
"Failed to send firmware data (%d)",
|
|
err);
|
|
goto done;
|
|
}
|
|
|
|
fw_ptr += frag_len;
|
|
frag_len = 0;
|
|
}
|
|
}
|
|
|
|
done:
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL_GPL(btintel_download_firmware);
|
|
|
|
void btintel_reset_to_bootloader(struct hci_dev *hdev)
|
|
{
|
|
struct intel_reset params;
|
|
struct sk_buff *skb;
|
|
|
|
/* Send Intel Reset command. This will result in
|
|
* re-enumeration of BT controller.
|
|
*
|
|
* Intel Reset parameter description:
|
|
* reset_type : 0x00 (Soft reset),
|
|
* 0x01 (Hard reset)
|
|
* patch_enable : 0x00 (Do not enable),
|
|
* 0x01 (Enable)
|
|
* ddc_reload : 0x00 (Do not reload),
|
|
* 0x01 (Reload)
|
|
* boot_option: 0x00 (Current image),
|
|
* 0x01 (Specified boot address)
|
|
* boot_param: Boot address
|
|
*
|
|
*/
|
|
params.reset_type = 0x01;
|
|
params.patch_enable = 0x01;
|
|
params.ddc_reload = 0x01;
|
|
params.boot_option = 0x00;
|
|
params.boot_param = cpu_to_le32(0x00000000);
|
|
|
|
skb = __hci_cmd_sync(hdev, 0xfc01, sizeof(params),
|
|
¶ms, HCI_INIT_TIMEOUT);
|
|
if (IS_ERR(skb)) {
|
|
bt_dev_err(hdev, "FW download error recovery failed (%ld)",
|
|
PTR_ERR(skb));
|
|
return;
|
|
}
|
|
bt_dev_info(hdev, "Intel reset sent to retry FW download");
|
|
kfree_skb(skb);
|
|
|
|
/* Current Intel BT controllers(ThP/JfP) hold the USB reset
|
|
* lines for 2ms when it receives Intel Reset in bootloader mode.
|
|
* Whereas, the upcoming Intel BT controllers will hold USB reset
|
|
* for 150ms. To keep the delay generic, 150ms is chosen here.
|
|
*/
|
|
msleep(150);
|
|
}
|
|
EXPORT_SYMBOL_GPL(btintel_reset_to_bootloader);
|
|
|
|
MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
|
|
MODULE_DESCRIPTION("Bluetooth support for Intel devices ver " VERSION);
|
|
MODULE_VERSION(VERSION);
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_FIRMWARE("intel/ibt-11-5.sfi");
|
|
MODULE_FIRMWARE("intel/ibt-11-5.ddc");
|
|
MODULE_FIRMWARE("intel/ibt-12-16.sfi");
|
|
MODULE_FIRMWARE("intel/ibt-12-16.ddc");
|