181 строка
5.3 KiB
C
181 строка
5.3 KiB
C
/*
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* FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
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*
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* Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This driver manages a bridge between an FPGA and the SDRAM used by the ARM
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* host processor system (HPS).
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*
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* The bridge contains 4 read ports, 4 write ports, and 6 command ports.
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* Reconfiguring these ports requires that no SDRAM transactions occur during
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* reconfiguration. The code reconfiguring the ports cannot run out of SDRAM
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* nor can the FPGA access the SDRAM during reconfiguration. This driver does
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* not support reconfiguring the ports. The ports are configured by code
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* running out of on chip ram before Linux is started and the configuration
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* is passed in a handoff register in the system manager.
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*
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* This driver supports enabling and disabling of the configured ports, which
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* allows for safe reprogramming of the FPGA, assuming that the new FPGA image
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* uses the same port configuration. Bridges must be disabled before
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* reprogramming the FPGA and re-enabled after the FPGA has been programmed.
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*/
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#include <linux/fpga/fpga-bridge.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80
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#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK 0x00003fff
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#define ALT_SDR_CTL_FPGAPORTRST_RD_SHIFT 0
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#define ALT_SDR_CTL_FPGAPORTRST_WR_SHIFT 4
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#define ALT_SDR_CTL_FPGAPORTRST_CTRL_SHIFT 8
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/*
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* From the Cyclone V HPS Memory Map document:
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* These registers are used to store handoff information between the
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* preloader and the OS. These 8 registers can be used to store any
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* information. The contents of these registers have no impact on
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* the state of the HPS hardware.
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*/
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#define SYSMGR_ISWGRP_HANDOFF3 (0x8C)
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#define F2S_BRIDGE_NAME "fpga2sdram"
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struct alt_fpga2sdram_data {
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struct device *dev;
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struct regmap *sdrctl;
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int mask;
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};
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static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge)
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{
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struct alt_fpga2sdram_data *priv = bridge->priv;
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int value;
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regmap_read(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, &value);
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return (value & priv->mask) == priv->mask;
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}
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static inline int _alt_fpga2sdram_enable_set(struct alt_fpga2sdram_data *priv,
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bool enable)
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{
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return regmap_update_bits(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST,
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priv->mask, enable ? priv->mask : 0);
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}
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static int alt_fpga2sdram_enable_set(struct fpga_bridge *bridge, bool enable)
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{
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return _alt_fpga2sdram_enable_set(bridge->priv, enable);
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}
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struct prop_map {
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char *prop_name;
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u32 *prop_value;
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u32 prop_max;
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};
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static const struct fpga_bridge_ops altera_fpga2sdram_br_ops = {
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.enable_set = alt_fpga2sdram_enable_set,
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.enable_show = alt_fpga2sdram_enable_show,
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};
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static const struct of_device_id altera_fpga_of_match[] = {
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{ .compatible = "altr,socfpga-fpga2sdram-bridge" },
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{},
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};
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static int alt_fpga_bridge_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct alt_fpga2sdram_data *priv;
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u32 enable;
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struct regmap *sysmgr;
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int ret = 0;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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priv->sdrctl = syscon_regmap_lookup_by_compatible("altr,sdr-ctl");
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if (IS_ERR(priv->sdrctl)) {
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dev_err(dev, "regmap for altr,sdr-ctl lookup failed.\n");
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return PTR_ERR(priv->sdrctl);
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}
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sysmgr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
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if (IS_ERR(sysmgr)) {
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dev_err(dev, "regmap for altr,sys-mgr lookup failed.\n");
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return PTR_ERR(sysmgr);
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}
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/* Get f2s bridge configuration saved in handoff register */
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regmap_read(sysmgr, SYSMGR_ISWGRP_HANDOFF3, &priv->mask);
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ret = fpga_bridge_register(dev, F2S_BRIDGE_NAME,
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&altera_fpga2sdram_br_ops, priv);
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if (ret)
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return ret;
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dev_info(dev, "driver initialized with handoff %08x\n", priv->mask);
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if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) {
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if (enable > 1) {
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dev_warn(dev, "invalid bridge-enable %u > 1\n", enable);
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} else {
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dev_info(dev, "%s bridge\n",
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(enable ? "enabling" : "disabling"));
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ret = _alt_fpga2sdram_enable_set(priv, enable);
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if (ret) {
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fpga_bridge_unregister(&pdev->dev);
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return ret;
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}
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}
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}
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return ret;
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}
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static int alt_fpga_bridge_remove(struct platform_device *pdev)
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{
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fpga_bridge_unregister(&pdev->dev);
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return 0;
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}
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MODULE_DEVICE_TABLE(of, altera_fpga_of_match);
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static struct platform_driver altera_fpga_driver = {
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.probe = alt_fpga_bridge_probe,
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.remove = alt_fpga_bridge_remove,
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.driver = {
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.name = "altera_fpga2sdram_bridge",
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.of_match_table = of_match_ptr(altera_fpga_of_match),
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},
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};
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module_platform_driver(altera_fpga_driver);
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MODULE_DESCRIPTION("Altera SoCFPGA FPGA to SDRAM Bridge");
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MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
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MODULE_LICENSE("GPL v2");
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