Suzuki K Poulose 50ed0188af arm64: Add work around for Arm Cortex-A55 Erratum 1024718 ... commit ece1397cbc upstream. Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer from an erratum 1024718, which causes incorrect updates when DBM/AP bits in a page table entry is modified without a break-before-make sequence. The work around is to skip enabling the hardware DBM feature on the affected cores. The hardware Access Flag management features is not affected. There are some other cores suffering from this errata, which could be added to the midr_list to trigger the work around. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: ckadabi@codeaurora.org Reviewed-by: Dave Martin <dave.martin@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2018-05-16 10:10:25 +02:00
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acpi_object_usage.txt	ARM64: ACPI: Update documentation for latest specification version	2016-06-21 16:26:09 +01:00
arm-acpi.txt	ARM64: ACPI: Update documentation for latest specification version	2016-06-21 16:26:09 +01:00
booting.txt	arm64: add the initrd region to the linear mapping explicitly	2016-04-14 16:20:45 +01:00
cpu-feature-registers.txt	arm64: Expose DC CVAP to userspace	2017-08-09 11:00:35 +01:00
legacy_instructions.txt	arm64: Emulate SETEND for AArch32 tasks	2015-01-23 17:11:44 +00:00
memory.txt	Documentation/arm64/memory.txt: fix typo	2014-10-20 17:55:38 +01:00
silicon-errata.txt	arm64: Add work around for Arm Cortex-A55 Erratum 1024718	2018-05-16 10:10:25 +02:00
tagged-pointers.txt	arm64: documentation: document tagged pointer stack constraints	2017-05-09 17:43:18 +01:00