433 строки
11 KiB
C
433 строки
11 KiB
C
/*
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* arch/arm/mach-lpc32xx/irq.c
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <mach/irqs.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "common.h"
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/*
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* Default value representing the Activation polarity of all internal
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* interrupt sources
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*/
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#define MIC_APR_DEFAULT 0x3FF0EFE0
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#define SIC1_APR_DEFAULT 0xFBD27186
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#define SIC2_APR_DEFAULT 0x801810C0
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/*
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* Default value representing the Activation Type of all internal
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* interrupt sources. All are level sensitive.
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*/
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#define MIC_ATR_DEFAULT 0x00000000
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#define SIC1_ATR_DEFAULT 0x00026000
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#define SIC2_ATR_DEFAULT 0x00000000
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struct lpc32xx_event_group_regs {
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void __iomem *enab_reg;
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void __iomem *edge_reg;
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void __iomem *maskstat_reg;
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void __iomem *rawstat_reg;
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};
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static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = {
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.enab_reg = LPC32XX_CLKPWR_INT_ER,
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.edge_reg = LPC32XX_CLKPWR_INT_AP,
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.maskstat_reg = LPC32XX_CLKPWR_INT_SR,
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.rawstat_reg = LPC32XX_CLKPWR_INT_RS,
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};
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static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = {
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.enab_reg = LPC32XX_CLKPWR_PIN_ER,
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.edge_reg = LPC32XX_CLKPWR_PIN_AP,
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.maskstat_reg = LPC32XX_CLKPWR_PIN_SR,
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.rawstat_reg = LPC32XX_CLKPWR_PIN_RS,
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};
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struct lpc32xx_event_info {
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const struct lpc32xx_event_group_regs *event_group;
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u32 mask;
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};
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/*
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* Maps an IRQ number to and event mask and register
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*/
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static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
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[IRQ_LPC32XX_GPI_08] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
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},
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[IRQ_LPC32XX_GPI_09] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
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},
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[IRQ_LPC32XX_GPI_19] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
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},
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[IRQ_LPC32XX_GPI_07] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
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},
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[IRQ_LPC32XX_GPI_00] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
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},
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[IRQ_LPC32XX_GPI_01] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
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},
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[IRQ_LPC32XX_GPI_02] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
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},
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[IRQ_LPC32XX_GPI_03] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
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},
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[IRQ_LPC32XX_GPI_04] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
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},
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[IRQ_LPC32XX_GPI_05] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
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},
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[IRQ_LPC32XX_GPI_06] = {
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.event_group = &lpc32xx_event_pin_regs,
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.mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
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},
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[IRQ_LPC32XX_GPIO_00] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
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},
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[IRQ_LPC32XX_GPIO_01] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
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},
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[IRQ_LPC32XX_GPIO_02] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
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},
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[IRQ_LPC32XX_GPIO_03] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
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},
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[IRQ_LPC32XX_GPIO_04] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
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},
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[IRQ_LPC32XX_GPIO_05] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
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},
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[IRQ_LPC32XX_KEY] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
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},
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[IRQ_LPC32XX_USB_OTG_ATX] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
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},
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[IRQ_LPC32XX_USB_HOST] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
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},
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[IRQ_LPC32XX_RTC] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
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},
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[IRQ_LPC32XX_MSTIMER] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
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},
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[IRQ_LPC32XX_TS_AUX] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
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},
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[IRQ_LPC32XX_TS_P] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
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},
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[IRQ_LPC32XX_TS_IRQ] = {
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.event_group = &lpc32xx_event_int_regs,
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.mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
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},
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};
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static void get_controller(unsigned int irq, unsigned int *base,
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unsigned int *irqbit)
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{
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if (irq < 32) {
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*base = LPC32XX_MIC_BASE;
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*irqbit = 1 << irq;
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} else if (irq < 64) {
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*base = LPC32XX_SIC1_BASE;
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*irqbit = 1 << (irq - 32);
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} else {
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*base = LPC32XX_SIC2_BASE;
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*irqbit = 1 << (irq - 64);
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}
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}
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static void lpc32xx_mask_irq(struct irq_data *d)
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{
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unsigned int reg, ctrl, mask;
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get_controller(d->irq, &ctrl, &mask);
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reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
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__raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
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}
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static void lpc32xx_unmask_irq(struct irq_data *d)
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{
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unsigned int reg, ctrl, mask;
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get_controller(d->irq, &ctrl, &mask);
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reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
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__raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
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}
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static void lpc32xx_ack_irq(struct irq_data *d)
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{
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unsigned int ctrl, mask;
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get_controller(d->irq, &ctrl, &mask);
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__raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
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/* Also need to clear pending wake event */
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if (lpc32xx_events[d->irq].mask != 0)
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__raw_writel(lpc32xx_events[d->irq].mask,
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lpc32xx_events[d->irq].event_group->rawstat_reg);
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}
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static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
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int use_edge)
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{
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unsigned int reg, ctrl, mask;
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get_controller(irq, &ctrl, &mask);
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/* Activation level, high or low */
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reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl));
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if (use_high_level)
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reg |= mask;
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else
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reg &= ~mask;
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__raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));
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/* Activation type, edge or level */
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reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl));
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if (use_edge)
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reg |= mask;
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else
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reg &= ~mask;
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__raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
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/* Use same polarity for the wake events */
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if (lpc32xx_events[irq].mask != 0) {
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reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg);
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if (use_high_level)
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reg |= lpc32xx_events[irq].mask;
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else
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reg &= ~lpc32xx_events[irq].mask;
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__raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);
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}
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}
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static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
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{
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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/* Rising edge sensitive */
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__lpc32xx_set_irq_type(d->irq, 1, 1);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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/* Falling edge sensitive */
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__lpc32xx_set_irq_type(d->irq, 0, 1);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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/* Low level sensitive */
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__lpc32xx_set_irq_type(d->irq, 0, 0);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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/* High level sensitive */
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__lpc32xx_set_irq_type(d->irq, 1, 0);
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break;
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/* Other modes are not supported */
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default:
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return -EINVAL;
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}
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/* Ok to use the level handler for all types */
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irq_set_handler(d->irq, handle_level_irq);
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return 0;
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}
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static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
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{
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unsigned long eventreg;
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if (lpc32xx_events[d->irq].mask != 0) {
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eventreg = __raw_readl(lpc32xx_events[d->irq].
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event_group->enab_reg);
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if (state)
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eventreg |= lpc32xx_events[d->irq].mask;
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else
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eventreg &= ~lpc32xx_events[d->irq].mask;
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__raw_writel(eventreg,
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lpc32xx_events[d->irq].event_group->enab_reg);
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return 0;
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}
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/* Clear event */
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__raw_writel(lpc32xx_events[d->irq].mask,
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lpc32xx_events[d->irq].event_group->rawstat_reg);
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return -ENODEV;
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}
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static void __init lpc32xx_set_default_mappings(unsigned int apr,
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unsigned int atr, unsigned int offset)
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{
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unsigned int i;
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/* Set activation levels for each interrupt */
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i = 0;
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while (i < 32) {
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__lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1),
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((atr >> i) & 0x1));
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i++;
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}
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}
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static struct irq_chip lpc32xx_irq_chip = {
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.irq_ack = lpc32xx_ack_irq,
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.irq_mask = lpc32xx_mask_irq,
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.irq_unmask = lpc32xx_unmask_irq,
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.irq_set_type = lpc32xx_set_irq_type,
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.irq_set_wake = lpc32xx_irq_wake
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};
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static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
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while (ints != 0) {
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int irqno = fls(ints) - 1;
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ints &= ~(1 << irqno);
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generic_handle_irq(LPC32XX_SIC1_IRQ(irqno));
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}
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}
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static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
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while (ints != 0) {
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int irqno = fls(ints) - 1;
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ints &= ~(1 << irqno);
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generic_handle_irq(LPC32XX_SIC2_IRQ(irqno));
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}
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}
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void __init lpc32xx_init_irq(void)
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{
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unsigned int i;
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/* Setup MIC */
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__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
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__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));
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__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));
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/* Setup SIC1 */
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__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
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__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
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__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
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/* Setup SIC2 */
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__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
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__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
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__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
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/* Configure supported IRQ's */
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for (i = 0; i < NR_IRQS; i++) {
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irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
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handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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/* Set default mappings */
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lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0);
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lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
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lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
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/* mask all interrupts except SUBIRQ */
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__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
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__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
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__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
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/* MIC SUBIRQx interrupts will route handling to the chain handlers */
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irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
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irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
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/* Initially disable all wake events */
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__raw_writel(0, LPC32XX_CLKPWR_P01_ER);
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__raw_writel(0, LPC32XX_CLKPWR_INT_ER);
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__raw_writel(0, LPC32XX_CLKPWR_PIN_ER);
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/*
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* Default wake activation polarities, all pin sources are low edge
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* triggered
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*/
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__raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |
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LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT |
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LPC32XX_CLKPWR_INTSRC_RTC_BIT,
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LPC32XX_CLKPWR_INT_AP);
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__raw_writel(0, LPC32XX_CLKPWR_PIN_AP);
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/* Clear latched wake event states */
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__raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),
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LPC32XX_CLKPWR_PIN_RS);
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__raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
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LPC32XX_CLKPWR_INT_RS);
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}
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