441 строка
12 KiB
C
441 строка
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell
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*
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* Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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*
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* This file helps PCI controller drivers implement a fake root port
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* PCI bridge when the HW doesn't provide such a root port PCI
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* bridge.
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*
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* It emulates a PCI bridge by providing a fake PCI configuration
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* space (and optionally a PCIe capability configuration space) in
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* memory. By default the read/write operations simply read and update
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* this fake configuration space in memory. However, PCI controller
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* drivers can provide through the 'struct pci_sw_bridge_ops'
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* structure a set of operations to override or complement this
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* default behavior.
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*/
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#include <linux/pci.h>
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#include "pci-bridge-emul.h"
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#define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF
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#define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END
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#define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2)
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struct pci_bridge_reg_behavior {
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/* Read-only bits */
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u32 ro;
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/* Read-write bits */
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u32 rw;
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/* Write-1-to-clear bits */
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u32 w1c;
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/* Reserved bits (hardwired to 0) */
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u32 rsvd;
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};
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const static struct pci_bridge_reg_behavior pci_regs_behavior[] = {
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[PCI_VENDOR_ID / 4] = { .ro = ~0 },
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[PCI_COMMAND / 4] = {
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.rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
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PCI_COMMAND_SERR),
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.ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
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PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
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PCI_COMMAND_FAST_BACK) |
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(PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
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PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
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.rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16),
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.w1c = (PCI_STATUS_PARITY |
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PCI_STATUS_SIG_TARGET_ABORT |
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PCI_STATUS_REC_TARGET_ABORT |
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PCI_STATUS_REC_MASTER_ABORT |
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PCI_STATUS_SIG_SYSTEM_ERROR |
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PCI_STATUS_DETECTED_PARITY) << 16,
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},
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[PCI_CLASS_REVISION / 4] = { .ro = ~0 },
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/*
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* Cache Line Size register: implement as read-only, we do not
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* pretend implementing "Memory Write and Invalidate"
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* transactions"
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*
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* Latency Timer Register: implemented as read-only, as "A
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* bridge that is not capable of a burst transfer of more than
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* two data phases on its primary interface is permitted to
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* hardwire the Latency Timer to a value of 16 or less"
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*
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* Header Type: always read-only
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*
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* BIST register: implemented as read-only, as "A bridge that
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* does not support BIST must implement this register as a
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* read-only register that returns 0 when read"
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*/
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[PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
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/*
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* Base Address registers not used must be implemented as
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* read-only registers that return 0 when read.
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*/
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[PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
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[PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
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[PCI_PRIMARY_BUS / 4] = {
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/* Primary, secondary and subordinate bus are RW */
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.rw = GENMASK(24, 0),
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/* Secondary latency is read-only */
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.ro = GENMASK(31, 24),
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},
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[PCI_IO_BASE / 4] = {
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/* The high four bits of I/O base/limit are RW */
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.rw = (GENMASK(15, 12) | GENMASK(7, 4)),
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/* The low four bits of I/O base/limit are RO */
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.ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
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PCI_STATUS_DEVSEL_MASK) << 16) |
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GENMASK(11, 8) | GENMASK(3, 0)),
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.w1c = (PCI_STATUS_PARITY |
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PCI_STATUS_SIG_TARGET_ABORT |
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PCI_STATUS_REC_TARGET_ABORT |
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PCI_STATUS_REC_MASTER_ABORT |
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PCI_STATUS_SIG_SYSTEM_ERROR |
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PCI_STATUS_DETECTED_PARITY) << 16,
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.rsvd = ((BIT(6) | GENMASK(4, 0)) << 16),
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},
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[PCI_MEMORY_BASE / 4] = {
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/* The high 12-bits of mem base/limit are RW */
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.rw = GENMASK(31, 20) | GENMASK(15, 4),
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/* The low four bits of mem base/limit are RO */
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.ro = GENMASK(19, 16) | GENMASK(3, 0),
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},
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[PCI_PREF_MEMORY_BASE / 4] = {
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/* The high 12-bits of pref mem base/limit are RW */
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.rw = GENMASK(31, 20) | GENMASK(15, 4),
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/* The low four bits of pref mem base/limit are RO */
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.ro = GENMASK(19, 16) | GENMASK(3, 0),
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},
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[PCI_PREF_BASE_UPPER32 / 4] = {
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.rw = ~0,
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},
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[PCI_PREF_LIMIT_UPPER32 / 4] = {
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.rw = ~0,
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},
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[PCI_IO_BASE_UPPER16 / 4] = {
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.rw = ~0,
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},
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[PCI_CAPABILITY_LIST / 4] = {
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.ro = GENMASK(7, 0),
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.rsvd = GENMASK(31, 8),
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},
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[PCI_ROM_ADDRESS1 / 4] = {
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.rw = GENMASK(31, 11) | BIT(0),
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.rsvd = GENMASK(10, 1),
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},
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/*
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* Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
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* are RO, and bridge control (31:16) are a mix of RW, RO,
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* reserved and W1C bits
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*/
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[PCI_INTERRUPT_LINE / 4] = {
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/* Interrupt line is RW */
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.rw = (GENMASK(7, 0) |
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((PCI_BRIDGE_CTL_PARITY |
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PCI_BRIDGE_CTL_SERR |
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PCI_BRIDGE_CTL_ISA |
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PCI_BRIDGE_CTL_VGA |
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PCI_BRIDGE_CTL_MASTER_ABORT |
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PCI_BRIDGE_CTL_BUS_RESET |
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BIT(8) | BIT(9) | BIT(11)) << 16)),
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/* Interrupt pin is RO */
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.ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
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.w1c = BIT(10) << 16,
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.rsvd = (GENMASK(15, 12) | BIT(4)) << 16,
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},
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};
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const static struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
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[PCI_CAP_LIST_ID / 4] = {
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/*
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* Capability ID, Next Capability Pointer and
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* Capabilities register are all read-only.
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*/
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.ro = ~0,
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},
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[PCI_EXP_DEVCAP / 4] = {
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.ro = ~0,
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},
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[PCI_EXP_DEVCTL / 4] = {
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/* Device control register is RW */
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.rw = GENMASK(15, 0),
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/*
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* Device status register has 4 bits W1C, then 2 bits
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* RO, the rest is reserved
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*/
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.w1c = GENMASK(19, 16),
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.ro = GENMASK(20, 19),
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.rsvd = GENMASK(31, 21),
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},
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[PCI_EXP_LNKCAP / 4] = {
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/* All bits are RO, except bit 23 which is reserved */
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.ro = lower_32_bits(~BIT(23)),
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.rsvd = BIT(23),
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},
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[PCI_EXP_LNKCTL / 4] = {
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/*
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* Link control has bits [1:0] and [11:3] RW, the
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* other bits are reserved.
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* Link status has bits [13:0] RO, and bits [14:15]
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* W1C.
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*/
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.rw = GENMASK(11, 3) | GENMASK(1, 0),
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.ro = GENMASK(13, 0) << 16,
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.w1c = GENMASK(15, 14) << 16,
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.rsvd = GENMASK(15, 12) | BIT(2),
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},
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[PCI_EXP_SLTCAP / 4] = {
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.ro = ~0,
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},
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[PCI_EXP_SLTCTL / 4] = {
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/*
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* Slot control has bits [12:0] RW, the rest is
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* reserved.
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*
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* Slot status has a mix of W1C and RO bits, as well
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* as reserved bits.
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*/
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.rw = GENMASK(12, 0),
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.w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
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PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
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PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
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.ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
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PCI_EXP_SLTSTA_EIS) << 16,
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.rsvd = GENMASK(15, 12) | (GENMASK(15, 9) << 16),
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},
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[PCI_EXP_RTCTL / 4] = {
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/*
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* Root control has bits [4:0] RW, the rest is
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* reserved.
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*
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* Root status has bit 0 RO, the rest is reserved.
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*/
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.rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
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PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
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PCI_EXP_RTCTL_CRSSVE),
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.ro = PCI_EXP_RTCAP_CRSVIS << 16,
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.rsvd = GENMASK(15, 5) | (GENMASK(15, 1) << 16),
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},
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[PCI_EXP_RTSTA / 4] = {
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.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
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.w1c = PCI_EXP_RTSTA_PME,
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.rsvd = GENMASK(31, 18),
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},
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};
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/*
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* Initialize a pci_bridge_emul structure to represent a fake PCI
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* bridge configuration space. The caller needs to have initialized
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* the PCI configuration space with whatever values make sense
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* (typically at least vendor, device, revision), the ->ops pointer,
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* and optionally ->data and ->has_pcie.
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*/
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int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
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unsigned int flags)
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{
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bridge->conf.class_revision |= PCI_CLASS_BRIDGE_PCI << 16;
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bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
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bridge->conf.cache_line_size = 0x10;
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bridge->conf.status = PCI_STATUS_CAP_LIST;
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bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
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sizeof(pci_regs_behavior),
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GFP_KERNEL);
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if (!bridge->pci_regs_behavior)
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return -ENOMEM;
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if (bridge->has_pcie) {
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bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
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bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
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/* Set PCIe v2, root port, slot support */
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bridge->pcie_conf.cap = PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
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PCI_EXP_FLAGS_SLOT;
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bridge->pcie_cap_regs_behavior =
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kmemdup(pcie_cap_regs_behavior,
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sizeof(pcie_cap_regs_behavior),
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GFP_KERNEL);
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if (!bridge->pcie_cap_regs_behavior) {
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kfree(bridge->pci_regs_behavior);
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return -ENOMEM;
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}
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}
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if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {
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bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
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bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
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}
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return 0;
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}
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/*
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* Cleanup a pci_bridge_emul structure that was previously initilized
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* using pci_bridge_emul_init().
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*/
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void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
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{
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if (bridge->has_pcie)
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kfree(bridge->pcie_cap_regs_behavior);
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kfree(bridge->pci_regs_behavior);
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}
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/*
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* Should be called by the PCI controller driver when reading the PCI
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* configuration space of the fake bridge. It will call back the
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* ->ops->read_base or ->ops->read_pcie operations.
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*/
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int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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int size, u32 *value)
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{
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int ret;
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int reg = where & ~3;
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pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
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int reg, u32 *value);
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u32 *cfgspace;
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const struct pci_bridge_reg_behavior *behavior;
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if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
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*value = 0;
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return PCIBIOS_SUCCESSFUL;
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}
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if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
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*value = 0;
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return PCIBIOS_SUCCESSFUL;
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}
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if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
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reg -= PCI_CAP_PCIE_START;
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read_op = bridge->ops->read_pcie;
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cfgspace = (u32 *) &bridge->pcie_conf;
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behavior = bridge->pcie_cap_regs_behavior;
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} else {
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read_op = bridge->ops->read_base;
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cfgspace = (u32 *) &bridge->conf;
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behavior = bridge->pci_regs_behavior;
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}
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if (read_op)
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ret = read_op(bridge, reg, value);
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else
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ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
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if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
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*value = cfgspace[reg / 4];
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/*
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* Make sure we never return any reserved bit with a value
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* different from 0.
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*/
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*value &= ~behavior[reg / 4].rsvd;
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if (size == 1)
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*value = (*value >> (8 * (where & 3))) & 0xff;
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else if (size == 2)
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*value = (*value >> (8 * (where & 3))) & 0xffff;
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else if (size != 4)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* Should be called by the PCI controller driver when writing the PCI
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* configuration space of the fake bridge. It will call back the
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* ->ops->write_base or ->ops->write_pcie operations.
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*/
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int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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int size, u32 value)
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{
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int reg = where & ~3;
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int mask, ret, old, new, shift;
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void (*write_op)(struct pci_bridge_emul *bridge, int reg,
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u32 old, u32 new, u32 mask);
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u32 *cfgspace;
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const struct pci_bridge_reg_behavior *behavior;
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if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
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return PCIBIOS_SUCCESSFUL;
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if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
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return PCIBIOS_SUCCESSFUL;
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shift = (where & 0x3) * 8;
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if (size == 4)
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mask = 0xffffffff;
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else if (size == 2)
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mask = 0xffff << shift;
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else if (size == 1)
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mask = 0xff << shift;
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
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reg -= PCI_CAP_PCIE_START;
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write_op = bridge->ops->write_pcie;
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cfgspace = (u32 *) &bridge->pcie_conf;
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behavior = bridge->pcie_cap_regs_behavior;
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} else {
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write_op = bridge->ops->write_base;
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cfgspace = (u32 *) &bridge->conf;
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behavior = bridge->pci_regs_behavior;
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}
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/* Keep all bits, except the RW bits */
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new = old & (~mask | ~behavior[reg / 4].rw);
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/* Update the value of the RW bits */
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new |= (value << shift) & (behavior[reg / 4].rw & mask);
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/* Clear the W1C bits */
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new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
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cfgspace[reg / 4] = new;
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if (write_op)
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write_op(bridge, reg, old, new, mask);
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return PCIBIOS_SUCCESSFUL;
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}
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