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WSL2-Linux-Kernel
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WSL2-Linux-Kernel/drivers/clk/rockchip
История
Johan Jonker caa2fd752e clk: rockchip: fix i2s gate bits on rk3066 and rk3188 
The Rockchip PX2/RK3066 uses these bits in CRU_CLKGATE7_CON:

hclk_i2s_8ch_gate_en  bit 4 (dtsi: i2s0)
hclk_i2s0_2ch_gate_en bit 2 (dtsi: i2s1)
hclk_i2s1_2ch_gate_en bit 3 (dtsi: i2s2)

The Rockchip PX3/RK3188 uses this bit in CRU_CLKGATE7_CON:

hclk_i2s_2ch_gate_en  bit 2 (dtsi: i2s0)

The bits got somehow mixed up in the clk-rk3188.c file.
The labels in the dtsi files are not suppose to change.
The sclk and hclk names should match for
"trace_event=clk_disable,clk_enable",
so remove GATE HCLK_I2S0 from the common clock tree and
fix the bits in the rk3066 and rk3188 clock tree.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20201118135822.9582-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 		2020-11-29 20:10:45 +01:00
..
Kconfig clk: rockchip: Add appropriate arch dependencies 2020-10-26 12:24:56 +01:00
Makefile clk: rockchip: fix the clk config to support module build 2020-09-22 15:16:38 +02:00
clk-cpu.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
clk-ddr.c clk: rockchip: Export rockchip_clk_register_ddrclk() 2020-09-22 15:16:37 +02:00
clk-half-divider.c clk: rockchip: Initialize hw to error to avoid undefined behavior 2020-10-07 19:08:38 -07:00
clk-inverter.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-mmc-phase.c clk: rockchip: fix mmc get phase 2020-03-06 12:06:01 -08:00
clk-muxgrf.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 2019-06-05 17:36:37 +02:00
clk-pll.c clk: rockchip: convert rk3036 pll type to use internal lock status 2020-06-15 11:47:16 +02:00
clk-px30.c clk: rockchip: protect the pclk_usb_grf as critical on px30 2019-11-05 20:53:42 +01:00
clk-rk3036.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-rk3128.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-rk3188.c clk: rockchip: fix i2s gate bits on rk3066 and rk3188 2020-11-29 20:10:45 +01:00
clk-rk3228.c clk: rockchip: Fix initialization of mux_pll_src_4plls_p 2020-08-18 20:09:02 -07:00
clk-rk3288.c clk: rockchip: use separate compatibles for rk3288w-cru 2020-07-05 12:18:29 +02:00
clk-rk3308.c clk: rockchip: rk3308: drop unused mux_timer_src_p 2020-09-22 14:36:20 +02:00
clk-rk3328.c clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328" 2020-07-08 16:22:10 +02:00
clk-rk3368.c This round of clk driver and framework updates is heavy on the driver update 2019-07-17 10:07:48 -07:00
clk-rk3399.c clk: rockchip: rk3399: Support module build 2020-09-22 15:16:54 +02:00
clk-rv1108.c clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver 2019-07-25 21:00:52 +02:00
clk.c clk: rockchip: Remove redundant null check before clk_prepare_enable 2020-11-29 20:02:58 +01:00
clk.h clk: rockchip: Add clock controller for the rk3308 2019-09-05 12:43:39 +02:00
softrst.c clk: rockchip: Export rockchip_register_softrst() 2020-09-22 15:16:38 +02:00