578 строки
14 KiB
C
578 строки
14 KiB
C
/*
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* Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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* Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
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*
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* Description:
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* General Purpose functions for the global management of the
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* QUICC Engine (QE).
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/bootmem.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/crc32.h>
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#include <asm/irq.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/immap_qe.h>
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#include <asm/qe.h>
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#include <asm/prom.h>
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#include <asm/rheap.h>
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static void qe_snums_init(void);
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static int qe_sdma_init(void);
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static DEFINE_SPINLOCK(qe_lock);
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DEFINE_SPINLOCK(cmxgcr_lock);
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EXPORT_SYMBOL(cmxgcr_lock);
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/* QE snum state */
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enum qe_snum_state {
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QE_SNUM_STATE_USED,
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QE_SNUM_STATE_FREE
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};
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/* QE snum */
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struct qe_snum {
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u8 num;
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enum qe_snum_state state;
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};
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/* We allocate this here because it is used almost exclusively for
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* the communication processor devices.
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*/
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struct qe_immap __iomem *qe_immr;
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EXPORT_SYMBOL(qe_immr);
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static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
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static phys_addr_t qebase = -1;
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phys_addr_t get_qe_base(void)
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{
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struct device_node *qe;
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int size;
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const u32 *prop;
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if (qebase != -1)
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return qebase;
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qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!qe) {
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qe = of_find_node_by_type(NULL, "qe");
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if (!qe)
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return qebase;
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}
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prop = of_get_property(qe, "reg", &size);
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if (prop && size >= sizeof(*prop))
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qebase = of_translate_address(qe, prop);
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of_node_put(qe);
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return qebase;
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}
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EXPORT_SYMBOL(get_qe_base);
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void __init qe_reset(void)
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{
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if (qe_immr == NULL)
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qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
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qe_snums_init();
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qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
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QE_CR_PROTOCOL_UNSPECIFIED, 0);
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/* Reclaim the MURAM memory for our use. */
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qe_muram_init();
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if (qe_sdma_init())
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panic("sdma init failed!");
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}
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int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
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{
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unsigned long flags;
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u8 mcn_shift = 0, dev_shift = 0;
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spin_lock_irqsave(&qe_lock, flags);
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if (cmd == QE_RESET) {
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out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
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} else {
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if (cmd == QE_ASSIGN_PAGE) {
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/* Here device is the SNUM, not sub-block */
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dev_shift = QE_CR_SNUM_SHIFT;
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} else if (cmd == QE_ASSIGN_RISC) {
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/* Here device is the SNUM, and mcnProtocol is
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* e_QeCmdRiscAssignment value */
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dev_shift = QE_CR_SNUM_SHIFT;
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mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
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} else {
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if (device == QE_CR_SUBBLOCK_USB)
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mcn_shift = QE_CR_MCN_USB_SHIFT;
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else
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mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
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}
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out_be32(&qe_immr->cp.cecdr, cmd_input);
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out_be32(&qe_immr->cp.cecr,
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(cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
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mcn_protocol << mcn_shift));
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}
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/* wait for the QE_CR_FLG to clear */
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while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG)
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cpu_relax();
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spin_unlock_irqrestore(&qe_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(qe_issue_cmd);
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/* Set a baud rate generator. This needs lots of work. There are
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* 16 BRGs, which can be connected to the QE channels or output
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* as clocks. The BRGs are in two different block of internal
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* memory mapped space.
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* The BRG clock is the QE clock divided by 2.
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* It was set up long ago during the initial boot phase and is
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* is given to us.
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* Baud rate clocks are zero-based in the driver code (as that maps
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* to port numbers). Documentation uses 1-based numbering.
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*/
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static unsigned int brg_clk = 0;
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unsigned int qe_get_brg_clk(void)
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{
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struct device_node *qe;
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int size;
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const u32 *prop;
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if (brg_clk)
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return brg_clk;
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qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!qe) {
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qe = of_find_node_by_type(NULL, "qe");
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if (!qe)
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return brg_clk;
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}
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prop = of_get_property(qe, "brg-frequency", &size);
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if (prop && size == sizeof(*prop))
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brg_clk = *prop;
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of_node_put(qe);
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return brg_clk;
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}
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EXPORT_SYMBOL(qe_get_brg_clk);
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/* Program the BRG to the given sampling rate and multiplier
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*
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* @brg: the BRG, QE_BRG1 - QE_BRG16
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* @rate: the desired sampling rate
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* @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
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* GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
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* then 'multiplier' should be 8.
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*/
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int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
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{
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u32 divisor, tempval;
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u32 div16 = 0;
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if ((brg < QE_BRG1) || (brg > QE_BRG16))
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return -EINVAL;
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divisor = qe_get_brg_clk() / (rate * multiplier);
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if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
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div16 = QE_BRGC_DIV16;
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divisor /= 16;
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}
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/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
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that the BRG divisor must be even if you're not using divide-by-16
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mode. */
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if (!div16 && (divisor & 1))
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divisor++;
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tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
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QE_BRGC_ENABLE | div16;
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out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
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return 0;
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}
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EXPORT_SYMBOL(qe_setbrg);
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/* Convert a string to a QE clock source enum
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*
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* This function takes a string, typically from a property in the device
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* tree, and returns the corresponding "enum qe_clock" value.
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*/
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enum qe_clock qe_clock_source(const char *source)
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{
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unsigned int i;
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if (strcasecmp(source, "none") == 0)
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return QE_CLK_NONE;
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if (strncasecmp(source, "brg", 3) == 0) {
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i = simple_strtoul(source + 3, NULL, 10);
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if ((i >= 1) && (i <= 16))
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return (QE_BRG1 - 1) + i;
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else
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return QE_CLK_DUMMY;
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}
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if (strncasecmp(source, "clk", 3) == 0) {
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i = simple_strtoul(source + 3, NULL, 10);
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if ((i >= 1) && (i <= 24))
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return (QE_CLK1 - 1) + i;
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else
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return QE_CLK_DUMMY;
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}
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return QE_CLK_DUMMY;
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}
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EXPORT_SYMBOL(qe_clock_source);
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/* Initialize SNUMs (thread serial numbers) according to
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* QE Module Control chapter, SNUM table
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*/
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static void qe_snums_init(void)
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{
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int i;
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static const u8 snum_init[] = {
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0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
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0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
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0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
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0xD8, 0xD9, 0xE8, 0xE9,
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};
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for (i = 0; i < QE_NUM_OF_SNUM; i++) {
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snums[i].num = snum_init[i];
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snums[i].state = QE_SNUM_STATE_FREE;
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}
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}
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int qe_get_snum(void)
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{
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unsigned long flags;
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int snum = -EBUSY;
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int i;
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spin_lock_irqsave(&qe_lock, flags);
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for (i = 0; i < QE_NUM_OF_SNUM; i++) {
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if (snums[i].state == QE_SNUM_STATE_FREE) {
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snums[i].state = QE_SNUM_STATE_USED;
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snum = snums[i].num;
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break;
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}
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}
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spin_unlock_irqrestore(&qe_lock, flags);
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return snum;
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}
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EXPORT_SYMBOL(qe_get_snum);
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void qe_put_snum(u8 snum)
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{
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int i;
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for (i = 0; i < QE_NUM_OF_SNUM; i++) {
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if (snums[i].num == snum) {
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snums[i].state = QE_SNUM_STATE_FREE;
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break;
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}
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}
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}
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EXPORT_SYMBOL(qe_put_snum);
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static int qe_sdma_init(void)
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{
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struct sdma __iomem *sdma = &qe_immr->sdma;
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unsigned long sdma_buf_offset;
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if (!sdma)
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return -ENODEV;
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/* allocate 2 internal temporary buffers (512 bytes size each) for
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* the SDMA */
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sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
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if (IS_ERR_VALUE(sdma_buf_offset))
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return -ENOMEM;
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out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
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out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
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(0x1 << QE_SDMR_CEN_SHIFT)));
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return 0;
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}
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/* The maximum number of RISCs we support */
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#define MAX_QE_RISC 2
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/* Firmware information stored here for qe_get_firmware_info() */
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static struct qe_firmware_info qe_firmware_info;
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/*
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* Set to 1 if QE firmware has been uploaded, and therefore
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* qe_firmware_info contains valid data.
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*/
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static int qe_firmware_uploaded;
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/*
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* Upload a QE microcode
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*
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* This function is a worker function for qe_upload_firmware(). It does
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* the actual uploading of the microcode.
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*/
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static void qe_upload_microcode(const void *base,
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const struct qe_microcode *ucode)
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{
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const __be32 *code = base + be32_to_cpu(ucode->code_offset);
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unsigned int i;
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if (ucode->major || ucode->minor || ucode->revision)
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printk(KERN_INFO "qe-firmware: "
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"uploading microcode '%s' version %u.%u.%u\n",
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ucode->id, ucode->major, ucode->minor, ucode->revision);
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else
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printk(KERN_INFO "qe-firmware: "
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"uploading microcode '%s'\n", ucode->id);
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/* Use auto-increment */
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out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
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QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
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for (i = 0; i < be32_to_cpu(ucode->count); i++)
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out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
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}
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/*
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* Upload a microcode to the I-RAM at a specific address.
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*
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* See Documentation/powerpc/qe-firmware.txt for information on QE microcode
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* uploading.
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*
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* Currently, only version 1 is supported, so the 'version' field must be
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* set to 1.
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*
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* The SOC model and revision are not validated, they are only displayed for
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* informational purposes.
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*
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* 'calc_size' is the calculated size, in bytes, of the firmware structure and
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* all of the microcode structures, minus the CRC.
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*
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* 'length' is the size that the structure says it is, including the CRC.
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*/
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int qe_upload_firmware(const struct qe_firmware *firmware)
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{
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unsigned int i;
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unsigned int j;
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u32 crc;
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size_t calc_size = sizeof(struct qe_firmware);
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size_t length;
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const struct qe_header *hdr;
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if (!firmware) {
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printk(KERN_ERR "qe-firmware: invalid pointer\n");
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return -EINVAL;
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}
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hdr = &firmware->header;
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length = be32_to_cpu(hdr->length);
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/* Check the magic */
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if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
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(hdr->magic[2] != 'F')) {
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printk(KERN_ERR "qe-firmware: not a microcode\n");
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return -EPERM;
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}
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/* Check the version */
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if (hdr->version != 1) {
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printk(KERN_ERR "qe-firmware: unsupported version\n");
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return -EPERM;
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}
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/* Validate some of the fields */
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if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
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printk(KERN_ERR "qe-firmware: invalid data\n");
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return -EINVAL;
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}
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/* Validate the length and check if there's a CRC */
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calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
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for (i = 0; i < firmware->count; i++)
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/*
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* For situations where the second RISC uses the same microcode
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* as the first, the 'code_offset' and 'count' fields will be
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* zero, so it's okay to add those.
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*/
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calc_size += sizeof(__be32) *
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be32_to_cpu(firmware->microcode[i].count);
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/* Validate the length */
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if (length != calc_size + sizeof(__be32)) {
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printk(KERN_ERR "qe-firmware: invalid length\n");
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return -EPERM;
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}
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/* Validate the CRC */
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crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
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if (crc != crc32(0, firmware, calc_size)) {
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printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
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return -EIO;
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}
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/*
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* If the microcode calls for it, split the I-RAM.
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*/
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if (!firmware->split)
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setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
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if (firmware->soc.model)
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printk(KERN_INFO
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"qe-firmware: firmware '%s' for %u V%u.%u\n",
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firmware->id, be16_to_cpu(firmware->soc.model),
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firmware->soc.major, firmware->soc.minor);
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else
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printk(KERN_INFO "qe-firmware: firmware '%s'\n",
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firmware->id);
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/*
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* The QE only supports one microcode per RISC, so clear out all the
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* saved microcode information and put in the new.
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*/
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memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
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strcpy(qe_firmware_info.id, firmware->id);
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qe_firmware_info.extended_modes = firmware->extended_modes;
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memcpy(qe_firmware_info.vtraps, firmware->vtraps,
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sizeof(firmware->vtraps));
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/* Loop through each microcode. */
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for (i = 0; i < firmware->count; i++) {
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const struct qe_microcode *ucode = &firmware->microcode[i];
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/* Upload a microcode if it's present */
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if (ucode->code_offset)
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qe_upload_microcode(firmware, ucode);
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/* Program the traps for this processor */
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for (j = 0; j < 16; j++) {
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u32 trap = be32_to_cpu(ucode->traps[j]);
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if (trap)
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out_be32(&qe_immr->rsp[i].tibcr[j], trap);
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}
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/* Enable traps */
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out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
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}
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qe_firmware_uploaded = 1;
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|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(qe_upload_firmware);
|
|
|
|
/*
|
|
* Get info on the currently-loaded firmware
|
|
*
|
|
* This function also checks the device tree to see if the boot loader has
|
|
* uploaded a firmware already.
|
|
*/
|
|
struct qe_firmware_info *qe_get_firmware_info(void)
|
|
{
|
|
static int initialized;
|
|
struct property *prop;
|
|
struct device_node *qe;
|
|
struct device_node *fw = NULL;
|
|
const char *sprop;
|
|
unsigned int i;
|
|
|
|
/*
|
|
* If we haven't checked yet, and a driver hasn't uploaded a firmware
|
|
* yet, then check the device tree for information.
|
|
*/
|
|
if (qe_firmware_uploaded)
|
|
return &qe_firmware_info;
|
|
|
|
if (initialized)
|
|
return NULL;
|
|
|
|
initialized = 1;
|
|
|
|
/*
|
|
* Newer device trees have an "fsl,qe" compatible property for the QE
|
|
* node, but we still need to support older device trees.
|
|
*/
|
|
qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
|
|
if (!qe) {
|
|
qe = of_find_node_by_type(NULL, "qe");
|
|
if (!qe)
|
|
return NULL;
|
|
}
|
|
|
|
/* Find the 'firmware' child node */
|
|
for_each_child_of_node(qe, fw) {
|
|
if (strcmp(fw->name, "firmware") == 0)
|
|
break;
|
|
}
|
|
|
|
of_node_put(qe);
|
|
|
|
/* Did we find the 'firmware' node? */
|
|
if (!fw)
|
|
return NULL;
|
|
|
|
qe_firmware_uploaded = 1;
|
|
|
|
/* Copy the data into qe_firmware_info*/
|
|
sprop = of_get_property(fw, "id", NULL);
|
|
if (sprop)
|
|
strncpy(qe_firmware_info.id, sprop,
|
|
sizeof(qe_firmware_info.id) - 1);
|
|
|
|
prop = of_find_property(fw, "extended-modes", NULL);
|
|
if (prop && (prop->length == sizeof(u64))) {
|
|
const u64 *iprop = prop->value;
|
|
|
|
qe_firmware_info.extended_modes = *iprop;
|
|
}
|
|
|
|
prop = of_find_property(fw, "virtual-traps", NULL);
|
|
if (prop && (prop->length == 32)) {
|
|
const u32 *iprop = prop->value;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
|
|
qe_firmware_info.vtraps[i] = iprop[i];
|
|
}
|
|
|
|
of_node_put(fw);
|
|
|
|
return &qe_firmware_info;
|
|
}
|
|
EXPORT_SYMBOL(qe_get_firmware_info);
|
|
|