390 строки
9.6 KiB
C
390 строки
9.6 KiB
C
/*
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* OMAP WakeupGen Source file
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*
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* OMAP WakeupGen is the interrupt controller extension used along
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* with ARM GIC to wake the CPU out from low power states on
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* external interrupts. It is responsible for generating wakeup
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* event from the incoming interrupts and enable bits. It is
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* implemented in MPU always ON power domain. During normal operation,
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* WakeupGen delivers external interrupts directly to the GIC.
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/cpu.h>
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#include <linux/notifier.h>
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#include <linux/cpu_pm.h>
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#include <asm/hardware/gic.h>
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#include <mach/omap-wakeupgen.h>
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#include <mach/omap-secure.h>
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#include "omap4-sar-layout.h"
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#include "common.h"
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#define NR_REG_BANKS 4
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#define MAX_IRQS 128
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#define WKG_MASK_ALL 0x00000000
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#define WKG_UNMASK_ALL 0xffffffff
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#define CPU_ENA_OFFSET 0x400
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#define CPU0_ID 0x0
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#define CPU1_ID 0x1
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static void __iomem *wakeupgen_base;
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static void __iomem *sar_base;
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static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
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static DEFINE_SPINLOCK(wakeupgen_lock);
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static unsigned int irq_target_cpu[NR_IRQS];
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/*
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* Static helper functions.
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*/
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static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
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{
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return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
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(cpu * CPU_ENA_OFFSET) + (idx * 4));
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}
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static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
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{
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__raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
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(cpu * CPU_ENA_OFFSET) + (idx * 4));
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}
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static inline void sar_writel(u32 val, u32 offset, u8 idx)
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{
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__raw_writel(val, sar_base + offset + (idx * 4));
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}
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static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
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{
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u8 i;
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for (i = 0; i < NR_REG_BANKS; i++)
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wakeupgen_writel(reg, i, cpu);
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}
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static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
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{
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unsigned int spi_irq;
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/*
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* PPIs and SGIs are not supported.
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*/
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if (irq < OMAP44XX_IRQ_GIC_START)
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return -EINVAL;
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/*
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* Subtract the GIC offset.
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*/
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spi_irq = irq - OMAP44XX_IRQ_GIC_START;
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if (spi_irq > MAX_IRQS) {
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pr_err("omap wakeupGen: Invalid IRQ%d\n", irq);
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return -EINVAL;
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}
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/*
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* Each WakeupGen register controls 32 interrupt.
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* i.e. 1 bit per SPI IRQ
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*/
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*reg_index = spi_irq >> 5;
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*bit_posn = spi_irq %= 32;
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return 0;
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}
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static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
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{
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u32 val, bit_number;
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u8 i;
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if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
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return;
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val = wakeupgen_readl(i, cpu);
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val &= ~BIT(bit_number);
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wakeupgen_writel(val, i, cpu);
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}
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static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
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{
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u32 val, bit_number;
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u8 i;
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if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
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return;
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val = wakeupgen_readl(i, cpu);
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val |= BIT(bit_number);
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wakeupgen_writel(val, i, cpu);
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}
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static void _wakeupgen_save_masks(unsigned int cpu)
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{
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u8 i;
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for (i = 0; i < NR_REG_BANKS; i++)
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per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
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}
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static void _wakeupgen_restore_masks(unsigned int cpu)
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{
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u8 i;
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for (i = 0; i < NR_REG_BANKS; i++)
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wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
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}
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/*
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* Architecture specific Mask extension
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*/
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static void wakeupgen_mask(struct irq_data *d)
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{
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unsigned long flags;
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spin_lock_irqsave(&wakeupgen_lock, flags);
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_wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
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spin_unlock_irqrestore(&wakeupgen_lock, flags);
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}
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/*
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* Architecture specific Unmask extension
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*/
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static void wakeupgen_unmask(struct irq_data *d)
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{
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unsigned long flags;
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spin_lock_irqsave(&wakeupgen_lock, flags);
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_wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
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spin_unlock_irqrestore(&wakeupgen_lock, flags);
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}
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/*
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* Mask or unmask all interrupts on given CPU.
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* 0 = Mask all interrupts on the 'cpu'
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* 1 = Unmask all interrupts on the 'cpu'
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* Ensure that the initial mask is maintained. This is faster than
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* iterating through GIC registers to arrive at the correct masks.
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*/
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static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
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{
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unsigned long flags;
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spin_lock_irqsave(&wakeupgen_lock, flags);
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if (set) {
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_wakeupgen_save_masks(cpu);
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_wakeupgen_set_all(cpu, WKG_MASK_ALL);
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} else {
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_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
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_wakeupgen_restore_masks(cpu);
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}
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spin_unlock_irqrestore(&wakeupgen_lock, flags);
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}
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#ifdef CONFIG_CPU_PM
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/*
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* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
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* ROM code. WakeupGen IP is integrated along with GIC to manage the
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* interrupt wakeups from CPU low power states. It manages
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* masking/unmasking of Shared peripheral interrupts(SPI). So the
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* interrupt enable/disable control should be in sync and consistent
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* at WakeupGen and GIC so that interrupts are not lost.
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*/
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static void irq_save_context(void)
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{
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u32 i, val;
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if (omap_rev() == OMAP4430_REV_ES1_0)
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return;
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if (!sar_base)
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sar_base = omap4_get_sar_ram_base();
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for (i = 0; i < NR_REG_BANKS; i++) {
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/* Save the CPUx interrupt mask for IRQ 0 to 127 */
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val = wakeupgen_readl(i, 0);
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sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
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val = wakeupgen_readl(i, 1);
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sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
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/*
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* Disable the secure interrupts for CPUx. The restore
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* code blindly restores secure and non-secure interrupt
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* masks from SAR RAM. Secure interrupts are not suppose
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* to be enabled from HLOS. So overwrite the SAR location
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* so that the secure interrupt remains disabled.
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*/
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sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
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sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
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}
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/* Save AuxBoot* registers */
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val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
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val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
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/* Save SyncReq generation logic */
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val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
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val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
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/* Save SyncReq generation logic */
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val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
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__raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
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val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
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__raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
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/* Set the Backup Bit Mask status */
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val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
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val |= SAR_BACKUP_STATUS_WAKEUPGEN;
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__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
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}
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/*
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* Clear WakeupGen SAR backup status.
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*/
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void irq_sar_clear(void)
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{
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u32 val;
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val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
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val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
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__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
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}
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/*
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* Save GIC and Wakeupgen interrupt context using secure API
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* for HS/EMU devices.
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*/
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static void irq_save_secure_context(void)
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{
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u32 ret;
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ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
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FLAG_START_CRITICAL,
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0, 0, 0, 0, 0);
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if (ret != API_HAL_RET_VALUE_OK)
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pr_err("GIC and Wakeupgen context save failed\n");
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}
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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unsigned int cpu = (unsigned int)hcpu;
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switch (action) {
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case CPU_ONLINE:
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wakeupgen_irqmask_all(cpu, 0);
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break;
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case CPU_DEAD:
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wakeupgen_irqmask_all(cpu, 1);
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block __refdata irq_hotplug_notifier = {
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.notifier_call = irq_cpu_hotplug_notify,
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};
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static void __init irq_hotplug_init(void)
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{
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register_hotcpu_notifier(&irq_hotplug_notifier);
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}
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#else
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static void __init irq_hotplug_init(void)
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{}
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#endif
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#ifdef CONFIG_CPU_PM
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static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
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{
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switch (cmd) {
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case CPU_CLUSTER_PM_ENTER:
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if (omap_type() == OMAP2_DEVICE_TYPE_GP)
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irq_save_context();
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else
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irq_save_secure_context();
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break;
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case CPU_CLUSTER_PM_EXIT:
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if (omap_type() == OMAP2_DEVICE_TYPE_GP)
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irq_sar_clear();
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block irq_notifier_block = {
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.notifier_call = irq_notifier,
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};
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static void __init irq_pm_init(void)
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{
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cpu_pm_register_notifier(&irq_notifier_block);
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}
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#else
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static void __init irq_pm_init(void)
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{}
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#endif
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/*
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* Initialise the wakeupgen module.
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*/
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int __init omap_wakeupgen_init(void)
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{
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int i;
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unsigned int boot_cpu = smp_processor_id();
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/* Not supported on OMAP4 ES1.0 silicon */
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
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return -EPERM;
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}
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/* Static mapping, never released */
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wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
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if (WARN_ON(!wakeupgen_base))
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return -ENOMEM;
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/* Clear all IRQ bitmasks at wakeupGen level */
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for (i = 0; i < NR_REG_BANKS; i++) {
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wakeupgen_writel(0, i, CPU0_ID);
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wakeupgen_writel(0, i, CPU1_ID);
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}
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/*
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* Override GIC architecture specific functions to add
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* OMAP WakeupGen interrupt controller along with GIC
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*/
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gic_arch_extn.irq_mask = wakeupgen_mask;
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gic_arch_extn.irq_unmask = wakeupgen_unmask;
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gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
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/*
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* FIXME: Add support to set_smp_affinity() once the core
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* GIC code has necessary hooks in place.
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*/
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/* Associate all the IRQs to boot CPU like GIC init does. */
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for (i = 0; i < NR_IRQS; i++)
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irq_target_cpu[i] = boot_cpu;
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irq_hotplug_init();
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irq_pm_init();
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return 0;
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}
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