396 строки
10 KiB
C
396 строки
10 KiB
C
/*
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* Copyright (C) 2013 BayHub Technology Ltd.
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*
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* Authors: Peter Guo <peter.guo@bayhubtech.com>
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* Adam Lee <adam.lee@canonical.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/pci.h>
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#include "sdhci.h"
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#include "sdhci-pci.h"
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#include "sdhci-pci-o2micro.h"
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static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
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{
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u32 scratch_32;
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pci_read_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, &scratch_32);
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scratch_32 &= 0x0000FFFF;
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scratch_32 |= value;
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pci_write_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, scratch_32);
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}
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static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
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{
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int ret;
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u32 scratch_32;
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/* Set led of SD host function enable */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG0, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~O2_SD_FREG0_LEDOFF;
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pci_write_config_dword(chip->pdev,
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O2_SD_FUNC_REG0, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_TEST_REG, &scratch_32);
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if (ret)
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return;
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scratch_32 |= O2_SD_LED_ENABLE;
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pci_write_config_dword(chip->pdev,
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O2_SD_TEST_REG, scratch_32);
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}
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void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
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{
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u32 scratch_32;
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int ret;
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/* Improve write performance for SD3.0 */
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ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
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pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
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/* Enable Link abnormal reset generating Reset */
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ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~((1 << 19) | (1 << 11));
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scratch_32 |= (1 << 10);
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pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
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/* set card power over current protection */
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ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
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if (ret)
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return;
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scratch_32 |= (1 << 4);
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pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
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/* adjust the output delay for SD mode */
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pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
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/* Set the output voltage setting of Aux 1.2v LDO */
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ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(3 << 12);
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pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
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/* Set Max power supply capability of SD host */
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ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x01FE);
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scratch_32 |= 0x00CC;
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pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
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/* Set DLL Tuning Window */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_TUNING_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x000000FF);
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scratch_32 |= 0x00000066;
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pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
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/* Set UHS2 T_EIDLE */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_UHS2_L1_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x000000FC);
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scratch_32 |= 0x00000084;
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pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
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/* Set UHS2 Termination */
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ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~((1 << 21) | (1 << 30));
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pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
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/* Set L1 Entrance Timer */
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ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0xf0000000);
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scratch_32 |= 0x30000000;
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pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_MISC_CTRL4, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x000f0000);
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scratch_32 |= 0x00080000;
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pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
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}
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EXPORT_SYMBOL_GPL(sdhci_pci_o2_fujin2_pci_init);
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int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
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{
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struct sdhci_pci_chip *chip;
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struct sdhci_host *host;
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u32 reg;
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chip = slot->chip;
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host = slot->host;
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switch (chip->pdev->device) {
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case PCI_DEVICE_ID_O2_SDS0:
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case PCI_DEVICE_ID_O2_SEABIRD0:
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case PCI_DEVICE_ID_O2_SEABIRD1:
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case PCI_DEVICE_ID_O2_SDS1:
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case PCI_DEVICE_ID_O2_FUJIN2:
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reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
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if (reg & 0x1)
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host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
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if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
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break;
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/* set dll watch dog timer */
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reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
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reg |= (1 << 12);
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sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
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break;
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default:
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break;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe_slot);
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int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
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{
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int ret;
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u8 scratch;
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u32 scratch_32;
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switch (chip->pdev->device) {
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case PCI_DEVICE_ID_O2_8220:
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case PCI_DEVICE_ID_O2_8221:
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case PCI_DEVICE_ID_O2_8320:
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case PCI_DEVICE_ID_O2_8321:
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/* This extra setup is required due to broken ADMA. */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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/* Set Multi 3 to VCC3V# */
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pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
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/* Disable CLK_REQ# support after media DET */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_CLKREQ, &scratch);
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if (ret)
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return ret;
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scratch |= 0x20;
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pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
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/* Choose capabilities, enable SDMA. We have to write 0x01
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* to the capabilities register first to unlock it.
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*/
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ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
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if (ret)
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return ret;
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scratch |= 0x01;
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pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
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pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
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/* Disable ADMA1/2 */
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pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
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pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
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/* Disable the infinite transfer mode */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_INF_MOD, &scratch);
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if (ret)
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return ret;
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scratch |= 0x08;
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pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
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/* Lock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch |= 0x80;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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break;
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case PCI_DEVICE_ID_O2_SDS0:
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case PCI_DEVICE_ID_O2_SDS1:
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case PCI_DEVICE_ID_O2_FUJIN2:
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/* UnLock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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/* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
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if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG0,
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&scratch_32);
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scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
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/* Check Whether subId is 0x11 or 0x12 */
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if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
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scratch_32 = 0x2c280000;
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/* Set Base Clock to 208MZ */
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o2_pci_set_baseclk(chip, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG4,
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&scratch_32);
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/* Enable Base Clk setting change */
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scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
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pci_write_config_dword(chip->pdev,
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O2_SD_FUNC_REG4,
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scratch_32);
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/* Set Tuning Window to 4 */
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pci_write_config_byte(chip->pdev,
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O2_SD_TUNING_CTRL, 0x44);
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break;
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}
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}
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/* Enable 8520 led function */
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o2_pci_led_enable(chip);
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/* Set timeout CLK */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_CLK_SETTING, &scratch_32);
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if (ret)
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return ret;
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scratch_32 &= ~(0xFF00);
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scratch_32 |= 0x07E0C800;
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pci_write_config_dword(chip->pdev,
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O2_SD_CLK_SETTING, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_CLKREQ, &scratch_32);
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if (ret)
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return ret;
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scratch_32 |= 0x3;
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pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, &scratch_32);
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if (ret)
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return ret;
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scratch_32 &= ~(0x1F3F070E);
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scratch_32 |= 0x18270106;
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pci_write_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, scratch_32);
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/* Disable UHS1 funciton */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_CAP_REG2, &scratch_32);
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if (ret)
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return ret;
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scratch_32 &= ~(0xE0);
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pci_write_config_dword(chip->pdev,
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O2_SD_CAP_REG2, scratch_32);
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if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
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sdhci_pci_o2_fujin2_pci_init(chip);
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/* Lock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch |= 0x80;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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break;
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case PCI_DEVICE_ID_O2_SEABIRD0:
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case PCI_DEVICE_ID_O2_SEABIRD1:
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/* UnLock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, &scratch_32);
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if ((scratch_32 & 0xff000000) == 0x01000000) {
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scratch_32 &= 0x0000FFFF;
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scratch_32 |= 0x1F340000;
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pci_write_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, scratch_32);
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} else {
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scratch_32 &= 0x0000FFFF;
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scratch_32 |= 0x2c280000;
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pci_write_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG4,
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&scratch_32);
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scratch_32 |= (1 << 22);
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pci_write_config_dword(chip->pdev,
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O2_SD_FUNC_REG4, scratch_32);
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}
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/* Set Tuning Windows to 5 */
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pci_write_config_byte(chip->pdev,
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O2_SD_TUNING_CTRL, 0x55);
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/* Lock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch |= 0x80;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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break;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe);
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int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
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{
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sdhci_pci_o2_probe(chip);
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return 0;
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}
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EXPORT_SYMBOL_GPL(sdhci_pci_o2_resume);
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