547 строки
14 KiB
C
547 строки
14 KiB
C
/*
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* Copyright(c) 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef _ADMA_H
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#define _ADMA_H
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#include <linux/types.h>
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#include <linux/io.h>
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#include <asm/hardware.h>
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#include <asm/hardware/iop_adma.h>
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#define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
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#define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
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#define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
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#define ADMA_IIPCR(chan) (chan->mmr_base + 0x18)
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#define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c)
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#define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20)
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#define ADMA_ANDAR(chan) (chan->mmr_base + 0x24)
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#define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
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#define ADMA_CARMD(chan) (chan->mmr_base + 0x2c)
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#define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
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#define ADMA_DLADR(chan) (chan->mmr_base + 0x34)
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#define ADMA_DUADR(chan) (chan->mmr_base + 0x38)
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#define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3)))
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#define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3)))
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struct iop13xx_adma_src {
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u32 src_addr;
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union {
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u32 upper_src_addr;
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struct {
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unsigned int pq_upper_src_addr:24;
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unsigned int pq_dmlt:8;
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};
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};
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};
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struct iop13xx_adma_desc_ctrl {
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unsigned int int_en:1;
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unsigned int xfer_dir:2;
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unsigned int src_select:4;
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unsigned int zero_result:1;
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unsigned int block_fill_en:1;
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unsigned int crc_gen_en:1;
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unsigned int crc_xfer_dis:1;
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unsigned int crc_seed_fetch_dis:1;
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unsigned int status_write_back_en:1;
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unsigned int endian_swap_en:1;
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unsigned int reserved0:2;
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unsigned int pq_update_xfer_en:1;
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unsigned int dual_xor_en:1;
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unsigned int pq_xfer_en:1;
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unsigned int p_xfer_dis:1;
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unsigned int reserved1:10;
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unsigned int relax_order_en:1;
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unsigned int no_snoop_en:1;
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};
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struct iop13xx_adma_byte_count {
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unsigned int byte_count:24;
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unsigned int host_if:3;
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unsigned int reserved:2;
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unsigned int zero_result_err_q:1;
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unsigned int zero_result_err:1;
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unsigned int tx_complete:1;
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};
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struct iop13xx_adma_desc_hw {
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u32 next_desc;
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union {
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u32 desc_ctrl;
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struct iop13xx_adma_desc_ctrl desc_ctrl_field;
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};
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union {
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u32 crc_addr;
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u32 block_fill_data;
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u32 q_dest_addr;
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};
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union {
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u32 byte_count;
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struct iop13xx_adma_byte_count byte_count_field;
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};
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union {
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u32 dest_addr;
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u32 p_dest_addr;
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};
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union {
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u32 upper_dest_addr;
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u32 pq_upper_dest_addr;
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};
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struct iop13xx_adma_src src[1];
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};
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struct iop13xx_adma_desc_dual_xor {
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u32 next_desc;
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u32 desc_ctrl;
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u32 reserved;
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u32 byte_count;
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u32 h_dest_addr;
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u32 h_upper_dest_addr;
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u32 src0_addr;
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u32 upper_src0_addr;
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u32 src1_addr;
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u32 upper_src1_addr;
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u32 h_src_addr;
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u32 h_upper_src_addr;
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u32 d_src_addr;
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u32 d_upper_src_addr;
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u32 d_dest_addr;
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u32 d_upper_dest_addr;
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};
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struct iop13xx_adma_desc_pq_update {
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u32 next_desc;
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u32 desc_ctrl;
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u32 reserved;
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u32 byte_count;
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u32 p_dest_addr;
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u32 p_upper_dest_addr;
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u32 src0_addr;
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u32 upper_src0_addr;
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u32 src1_addr;
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u32 upper_src1_addr;
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u32 p_src_addr;
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u32 p_upper_src_addr;
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u32 q_src_addr;
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struct {
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unsigned int q_upper_src_addr:24;
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unsigned int q_dmlt:8;
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};
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u32 q_dest_addr;
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u32 q_upper_dest_addr;
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};
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static inline int iop_adma_get_max_xor(void)
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{
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return 16;
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}
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static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
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{
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return __raw_readl(ADMA_ADAR(chan));
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}
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static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
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u32 next_desc_addr)
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{
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__raw_writel(next_desc_addr, ADMA_ANDAR(chan));
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}
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#define ADMA_STATUS_BUSY (1 << 13)
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static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
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{
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if (__raw_readl(ADMA_ACSR(chan)) &
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ADMA_STATUS_BUSY)
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return 1;
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else
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return 0;
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}
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static inline int
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iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
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{
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return 1;
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}
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#define iop_desc_is_aligned(x, y) 1
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static inline int
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iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
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{
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*slots_per_op = 1;
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return 1;
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}
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#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)
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static inline int
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iop_chan_memset_slot_count(size_t len, int *slots_per_op)
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{
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*slots_per_op = 1;
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return 1;
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}
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static inline int
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iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
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{
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int num_slots;
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/* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1
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* (1 source => 8 bytes) (1 slot => 32 bytes)
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*/
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num_slots = 1 + (((src_cnt - 1) << 3) >> 5);
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if (((src_cnt - 1) << 3) & 0x1f)
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num_slots++;
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*slots_per_op = num_slots;
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return num_slots;
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}
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#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
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#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
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static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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return hw_desc->dest_addr;
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}
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static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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return hw_desc->byte_count_field.byte_count;
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}
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static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan,
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int src_idx)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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return hw_desc->src[src_idx].src_addr;
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}
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static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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return hw_desc->desc_ctrl_field.src_select + 1;
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}
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static inline void
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iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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union {
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u32 value;
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struct iop13xx_adma_desc_ctrl field;
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} u_desc_ctrl;
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u_desc_ctrl.value = 0;
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u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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hw_desc->desc_ctrl = u_desc_ctrl.value;
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hw_desc->crc_addr = 0;
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}
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static inline void
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iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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union {
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u32 value;
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struct iop13xx_adma_desc_ctrl field;
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} u_desc_ctrl;
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u_desc_ctrl.value = 0;
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u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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u_desc_ctrl.field.block_fill_en = 1;
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u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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hw_desc->desc_ctrl = u_desc_ctrl.value;
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hw_desc->crc_addr = 0;
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}
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/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
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static inline void
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iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
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unsigned long flags)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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union {
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u32 value;
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struct iop13xx_adma_desc_ctrl field;
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} u_desc_ctrl;
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u_desc_ctrl.value = 0;
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u_desc_ctrl.field.src_select = src_cnt - 1;
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u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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hw_desc->desc_ctrl = u_desc_ctrl.value;
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hw_desc->crc_addr = 0;
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}
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#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
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/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
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static inline int
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iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
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unsigned long flags)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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union {
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u32 value;
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struct iop13xx_adma_desc_ctrl field;
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} u_desc_ctrl;
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u_desc_ctrl.value = 0;
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u_desc_ctrl.field.src_select = src_cnt - 1;
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u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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u_desc_ctrl.field.zero_result = 1;
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u_desc_ctrl.field.status_write_back_en = 1;
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u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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hw_desc->desc_ctrl = u_desc_ctrl.value;
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hw_desc->crc_addr = 0;
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return 1;
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}
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static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan,
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u32 byte_count)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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hw_desc->byte_count = byte_count;
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}
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static inline void
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iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
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{
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int slots_per_op = desc->slots_per_op;
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
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int i = 0;
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if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
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hw_desc->byte_count = len;
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} else {
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do {
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iter = iop_hw_desc_slot_idx(hw_desc, i);
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iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
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len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
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i += slots_per_op;
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} while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
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if (len) {
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iter = iop_hw_desc_slot_idx(hw_desc, i);
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iter->byte_count = len;
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}
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}
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}
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static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan,
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dma_addr_t addr)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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hw_desc->dest_addr = addr;
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hw_desc->upper_dest_addr = 0;
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}
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static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
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dma_addr_t addr)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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hw_desc->src[0].src_addr = addr;
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hw_desc->src[0].upper_src_addr = 0;
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}
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static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
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int src_idx, dma_addr_t addr)
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{
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int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
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int i = 0;
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do {
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iter = iop_hw_desc_slot_idx(hw_desc, i);
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iter->src[src_idx].src_addr = addr;
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iter->src[src_idx].upper_src_addr = 0;
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slot_cnt -= slots_per_op;
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if (slot_cnt) {
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i += slots_per_op;
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addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
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}
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} while (slot_cnt);
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}
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static inline void
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iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
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struct iop_adma_chan *chan)
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{
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iop_desc_init_memcpy(desc, 1);
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iop_desc_set_byte_count(desc, chan, 0);
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iop_desc_set_dest_addr(desc, chan, 0);
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iop_desc_set_memcpy_src_addr(desc, 0);
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}
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#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
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static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
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u32 next_desc_addr)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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BUG_ON(hw_desc->next_desc);
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hw_desc->next_desc = next_desc_addr;
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}
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static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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return hw_desc->next_desc;
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}
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static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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hw_desc->next_desc = 0;
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}
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static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
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u32 val)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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hw_desc->block_fill_data = val;
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}
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static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
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{
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struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
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struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;
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BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));
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if (desc_ctrl.pq_xfer_en)
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return byte_count.zero_result_err_q;
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else
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return byte_count.zero_result_err;
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}
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static inline void iop_chan_append(struct iop_adma_chan *chan)
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{
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u32 adma_accr;
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adma_accr = __raw_readl(ADMA_ACCR(chan));
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adma_accr |= 0x2;
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__raw_writel(adma_accr, ADMA_ACCR(chan));
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}
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static inline void iop_chan_idle(int busy, struct iop_adma_chan *chan)
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{
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do { } while (0);
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}
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static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
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{
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return __raw_readl(ADMA_ACSR(chan));
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}
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static inline void iop_chan_disable(struct iop_adma_chan *chan)
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{
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u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
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adma_chan_ctrl &= ~0x1;
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__raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
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}
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|
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static inline void iop_chan_enable(struct iop_adma_chan *chan)
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{
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u32 adma_chan_ctrl;
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|
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adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
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adma_chan_ctrl |= 0x1;
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__raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
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}
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|
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static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
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|
{
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|
u32 status = __raw_readl(ADMA_ACSR(chan));
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|
status &= (1 << 12);
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|
__raw_writel(status, ADMA_ACSR(chan));
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|
}
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|
|
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static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
|
|
{
|
|
u32 status = __raw_readl(ADMA_ACSR(chan));
|
|
status &= (1 << 11);
|
|
__raw_writel(status, ADMA_ACSR(chan));
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|
}
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|
|
|
static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
|
|
{
|
|
u32 status = __raw_readl(ADMA_ACSR(chan));
|
|
status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
|
|
__raw_writel(status, ADMA_ACSR(chan));
|
|
}
|
|
|
|
static inline int
|
|
iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
|
|
{
|
|
return test_bit(9, &status);
|
|
}
|
|
|
|
static inline int
|
|
iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
|
|
{
|
|
return test_bit(5, &status);
|
|
}
|
|
|
|
static inline int
|
|
iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
|
|
{
|
|
return test_bit(4, &status);
|
|
}
|
|
|
|
static inline int
|
|
iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
|
|
{
|
|
return test_bit(3, &status);
|
|
}
|
|
|
|
static inline int
|
|
iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int
|
|
iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int
|
|
iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#endif /* _ADMA_H */
|