Julia Lawall ea6c121321 RISC-V: KVM: fix typos in comments ... Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Anup Patel <anup@brainfault.org>		2022-06-09 09:18:15 +05:30
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Kconfig	riscv: do not select non-existing config ANON_INODES	2021-10-22 05:53:37 -04:00
Makefile	RISC-V: KVM: Add SBI HSM extension in KVM	2022-01-06 15:12:47 +05:30
main.c	RISC-V: KVM: Add Sv57x4 mode support for G-stage	2022-05-20 09:09:04 +05:30
mmu.c	RISC-V: KVM: Add remote HFENCE functions based on VCPU requests	2022-05-20 09:09:15 +05:30
tlb.c	RISC-V: KVM: Cleanup stale TLB entries when host CPU changes	2022-05-20 09:09:18 +05:30
vcpu.c	RISC-V: KVM: Introduce ISA extension register	2022-05-20 09:09:20 +05:30
vcpu_exit.c	RISC-V: KVM: Use G-stage name for hypervisor page table	2022-05-20 09:09:01 +05:30
vcpu_fp.c	RISC-V: KVM: include missing hwcap.h into vcpu_fp	2022-04-09 09:16:00 +05:30
vcpu_sbi.c	KVM: fix bad user ABI for KVM_EXIT_SYSTEM_EVENT	2022-04-29 12:38:22 -04:00
vcpu_sbi_base.c	RISC-V: KVM: Fix SBI implementation version	2022-02-02 18:58:06 +05:30
vcpu_sbi_hsm.c	RISC-V: KVM: Implement SBI HSM suspend call	2022-03-11 19:02:39 +05:30
vcpu_sbi_replace.c	RISC-V: KVM: Add remote HFENCE functions based on VCPU requests	2022-05-20 09:09:15 +05:30
vcpu_sbi_v01.c	RISC-V: KVM: Add remote HFENCE functions based on VCPU requests	2022-05-20 09:09:15 +05:30
vcpu_switch.S	RISC-V: KVM: Refine __kvm_riscv_switch_to() implementation	2022-03-11 19:02:22 +05:30
vcpu_timer.c	RISC-V: KVM: remove unneeded semicolon	2021-11-01 17:35:13 +05:30
vm.c	RISC-V: KVM: Use G-stage name for hypervisor page table	2022-05-20 09:09:01 +05:30
vmid.c	RISC-V: KVM: fix typos in comments	2022-06-09 09:18:15 +05:30