Levin Du 640332d1a0 clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 ... PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave from power on and the VDD_LOG is about 0.9V. When the kernel boots normally into the system, the PWM2 keeps outputing PWM signal. But the kernel hangs randomly after "Starting kernel ..." line on that board. When it happens, PWM2 outputs high level which causes VDD_LOG drops to 0.4V below the normal operating voltage. By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array, PWM clock is ensured to be prepared at startup and the PWM2 output is normal. After repeated tests, the early boot hang is gone. This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards. Signed-off-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2018-08-06 23:46:52 +02:00
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Makefile	clk: rockchip: add clock controller for px30	2018-07-06 19:17:57 +02:00
clk-cpu.c	clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk()	2017-09-28 15:22:50 +02:00
clk-ddr.c	clk: rockchip: don't return NULL when failing to register ddrclk branch	2016-10-16 02:39:58 +02:00
clk-half-divider.c	clk: rockchip: add support for half divider	2018-07-06 19:17:57 +02:00
clk-inverter.c	…
clk-mmc-phase.c	clk: rockchip: Fix error return in phase clock registration	2018-03-23 09:08:43 +01:00
clk-muxgrf.c	clk: rockchip: add a clock-type for muxes based in the grf	2017-01-02 14:24:57 +01:00
clk-pll.c	clk: rockchip: add pll_wait_lock for pll_enable	2017-03-22 18:33:22 +01:00
clk-px30.c	clk: rockchip: add clock controller for px30	2018-07-06 19:17:57 +02:00
clk-rk3036.c	clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036	2017-06-02 15:42:38 +02:00
clk-rk3128.c	clk: rockchip: add sclk_timer5 as critical clock on rk3128	2017-09-17 01:55:36 +02:00
clk-rk3188.c	clk: rockchip: use new cif/vdpu clock ids on rk3188	2017-10-14 21:32:11 +02:00
clk-rk3228.c	clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228	2018-03-23 08:49:35 +01:00
clk-rk3288.c	clk: rockchip: mark noc and some special clk as critical on rk3288	2017-06-02 15:54:20 +02:00
clk-rk3328.c	clk: rockchip: Fix wrong parents for MMC phase clock for rk3328	2018-03-23 08:58:19 +01:00
clk-rk3368.c	clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs	2017-10-14 21:31:58 +02:00
clk-rk3399.c	clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399	2018-08-06 23:46:52 +02:00
clk-rv1108.c	clk: rockchip: fix the rv1108 clk_mac sel register description	2017-08-22 02:55:03 +02:00
clk.c	clk: rockchip: add support for half divider	2018-07-06 19:17:57 +02:00
clk.h	clk: rockchip: add clock controller for px30	2018-07-06 19:17:57 +02:00
softrst.c	clk: rockchip: Make reset_control_ops const	2016-03-29 16:29:46 -07:00