701 строка
17 KiB
C
701 строка
17 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited. All rights reserved.
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*
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* Author: Leo Yan <leo.yan@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/amba/bus.h>
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#include <linux/coresight.h>
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#include <linux/cpu.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pm_qos.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include "coresight-priv.h"
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#define EDPCSR 0x0A0
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#define EDCIDSR 0x0A4
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#define EDVIDSR 0x0A8
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#define EDPCSR_HI 0x0AC
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#define EDOSLAR 0x300
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#define EDPRCR 0x310
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#define EDPRSR 0x314
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#define EDDEVID1 0xFC4
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#define EDDEVID 0xFC8
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#define EDPCSR_PROHIBITED 0xFFFFFFFF
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/* bits definition for EDPCSR */
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#define EDPCSR_THUMB BIT(0)
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#define EDPCSR_ARM_INST_MASK GENMASK(31, 2)
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#define EDPCSR_THUMB_INST_MASK GENMASK(31, 1)
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/* bits definition for EDPRCR */
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#define EDPRCR_COREPURQ BIT(3)
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#define EDPRCR_CORENPDRQ BIT(0)
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/* bits definition for EDPRSR */
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#define EDPRSR_DLK BIT(6)
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#define EDPRSR_PU BIT(0)
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/* bits definition for EDVIDSR */
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#define EDVIDSR_NS BIT(31)
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#define EDVIDSR_E2 BIT(30)
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#define EDVIDSR_E3 BIT(29)
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#define EDVIDSR_HV BIT(28)
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#define EDVIDSR_VMID GENMASK(7, 0)
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/*
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* bits definition for EDDEVID1:PSCROffset
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*
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* NOTE: armv8 and armv7 have different definition for the register,
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* so consolidate the bits definition as below:
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*
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* 0b0000 - Sample offset applies based on the instruction state, we
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* rely on EDDEVID to check if EDPCSR is implemented or not
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* 0b0001 - No offset applies.
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* 0b0010 - No offset applies, but do not use in AArch32 mode
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*
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*/
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#define EDDEVID1_PCSR_OFFSET_MASK GENMASK(3, 0)
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#define EDDEVID1_PCSR_OFFSET_INS_SET (0x0)
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#define EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32 (0x2)
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/* bits definition for EDDEVID */
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#define EDDEVID_PCSAMPLE_MODE GENMASK(3, 0)
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#define EDDEVID_IMPL_EDPCSR (0x1)
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#define EDDEVID_IMPL_EDPCSR_EDCIDSR (0x2)
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#define EDDEVID_IMPL_FULL (0x3)
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#define DEBUG_WAIT_SLEEP 1000
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#define DEBUG_WAIT_TIMEOUT 32000
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struct debug_drvdata {
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void __iomem *base;
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struct device *dev;
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int cpu;
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bool edpcsr_present;
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bool edcidsr_present;
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bool edvidsr_present;
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bool pc_has_offset;
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u32 edpcsr;
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u32 edpcsr_hi;
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u32 edprsr;
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u32 edvidsr;
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u32 edcidsr;
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};
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static DEFINE_MUTEX(debug_lock);
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static DEFINE_PER_CPU(struct debug_drvdata *, debug_drvdata);
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static int debug_count;
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static struct dentry *debug_debugfs_dir;
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static bool debug_enable;
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module_param_named(enable, debug_enable, bool, 0600);
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MODULE_PARM_DESC(enable, "Control to enable coresight CPU debug functionality");
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static void debug_os_unlock(struct debug_drvdata *drvdata)
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{
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/* Unlocks the debug registers */
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writel_relaxed(0x0, drvdata->base + EDOSLAR);
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/* Make sure the registers are unlocked before accessing */
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wmb();
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}
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/*
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* According to ARM DDI 0487A.k, before access external debug
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* registers should firstly check the access permission; if any
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* below condition has been met then cannot access debug
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* registers to avoid lockup issue:
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*
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* - CPU power domain is powered off;
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* - The OS Double Lock is locked;
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*
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* By checking EDPRSR can get to know if meet these conditions.
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*/
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static bool debug_access_permitted(struct debug_drvdata *drvdata)
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{
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/* CPU is powered off */
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if (!(drvdata->edprsr & EDPRSR_PU))
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return false;
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/* The OS Double Lock is locked */
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if (drvdata->edprsr & EDPRSR_DLK)
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return false;
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return true;
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}
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static void debug_force_cpu_powered_up(struct debug_drvdata *drvdata)
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{
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u32 edprcr;
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try_again:
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/*
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* Send request to power management controller and assert
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* DBGPWRUPREQ signal; if power management controller has
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* sane implementation, it should enable CPU power domain
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* in case CPU is in low power state.
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*/
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edprcr = readl_relaxed(drvdata->base + EDPRCR);
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edprcr |= EDPRCR_COREPURQ;
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writel_relaxed(edprcr, drvdata->base + EDPRCR);
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/* Wait for CPU to be powered up (timeout~=32ms) */
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if (readx_poll_timeout_atomic(readl_relaxed, drvdata->base + EDPRSR,
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drvdata->edprsr, (drvdata->edprsr & EDPRSR_PU),
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DEBUG_WAIT_SLEEP, DEBUG_WAIT_TIMEOUT)) {
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/*
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* Unfortunately the CPU cannot be powered up, so return
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* back and later has no permission to access other
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* registers. For this case, should disable CPU low power
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* states to ensure CPU power domain is enabled!
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*/
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dev_err(drvdata->dev, "%s: power up request for CPU%d failed\n",
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__func__, drvdata->cpu);
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return;
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}
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/*
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* At this point the CPU is powered up, so set the no powerdown
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* request bit so we don't lose power and emulate power down.
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*/
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edprcr = readl_relaxed(drvdata->base + EDPRCR);
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edprcr |= EDPRCR_COREPURQ | EDPRCR_CORENPDRQ;
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writel_relaxed(edprcr, drvdata->base + EDPRCR);
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drvdata->edprsr = readl_relaxed(drvdata->base + EDPRSR);
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/* The core power domain got switched off on use, try again */
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if (unlikely(!(drvdata->edprsr & EDPRSR_PU)))
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goto try_again;
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}
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static void debug_read_regs(struct debug_drvdata *drvdata)
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{
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u32 save_edprcr;
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CS_UNLOCK(drvdata->base);
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/* Unlock os lock */
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debug_os_unlock(drvdata);
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/* Save EDPRCR register */
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save_edprcr = readl_relaxed(drvdata->base + EDPRCR);
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/*
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* Ensure CPU power domain is enabled to let registers
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* are accessiable.
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*/
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debug_force_cpu_powered_up(drvdata);
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if (!debug_access_permitted(drvdata))
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goto out;
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drvdata->edpcsr = readl_relaxed(drvdata->base + EDPCSR);
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/*
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* As described in ARM DDI 0487A.k, if the processing
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* element (PE) is in debug state, or sample-based
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* profiling is prohibited, EDPCSR reads as 0xFFFFFFFF;
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* EDCIDSR, EDVIDSR and EDPCSR_HI registers also become
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* UNKNOWN state. So directly bail out for this case.
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*/
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if (drvdata->edpcsr == EDPCSR_PROHIBITED)
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goto out;
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/*
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* A read of the EDPCSR normally has the side-effect of
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* indirectly writing to EDCIDSR, EDVIDSR and EDPCSR_HI;
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* at this point it's safe to read value from them.
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*/
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if (IS_ENABLED(CONFIG_64BIT))
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drvdata->edpcsr_hi = readl_relaxed(drvdata->base + EDPCSR_HI);
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if (drvdata->edcidsr_present)
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drvdata->edcidsr = readl_relaxed(drvdata->base + EDCIDSR);
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if (drvdata->edvidsr_present)
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drvdata->edvidsr = readl_relaxed(drvdata->base + EDVIDSR);
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out:
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/* Restore EDPRCR register */
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writel_relaxed(save_edprcr, drvdata->base + EDPRCR);
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CS_LOCK(drvdata->base);
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}
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#ifdef CONFIG_64BIT
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static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata)
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{
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return (unsigned long)drvdata->edpcsr_hi << 32 |
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(unsigned long)drvdata->edpcsr;
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}
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#else
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static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata)
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{
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unsigned long arm_inst_offset = 0, thumb_inst_offset = 0;
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unsigned long pc;
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pc = (unsigned long)drvdata->edpcsr;
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if (drvdata->pc_has_offset) {
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arm_inst_offset = 8;
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thumb_inst_offset = 4;
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}
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/* Handle thumb instruction */
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if (pc & EDPCSR_THUMB) {
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pc = (pc & EDPCSR_THUMB_INST_MASK) - thumb_inst_offset;
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return pc;
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}
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/*
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* Handle arm instruction offset, if the arm instruction
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* is not 4 byte alignment then it's possible the case
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* for implementation defined; keep original value for this
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* case and print info for notice.
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*/
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if (pc & BIT(1))
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dev_emerg(drvdata->dev,
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"Instruction offset is implementation defined\n");
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else
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pc = (pc & EDPCSR_ARM_INST_MASK) - arm_inst_offset;
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return pc;
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}
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#endif
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static void debug_dump_regs(struct debug_drvdata *drvdata)
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{
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struct device *dev = drvdata->dev;
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unsigned long pc;
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dev_emerg(dev, " EDPRSR: %08x (Power:%s DLK:%s)\n",
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drvdata->edprsr,
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drvdata->edprsr & EDPRSR_PU ? "On" : "Off",
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drvdata->edprsr & EDPRSR_DLK ? "Lock" : "Unlock");
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if (!debug_access_permitted(drvdata)) {
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dev_emerg(dev, "No permission to access debug registers!\n");
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return;
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}
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if (drvdata->edpcsr == EDPCSR_PROHIBITED) {
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dev_emerg(dev, "CPU is in Debug state or profiling is prohibited!\n");
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return;
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}
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pc = debug_adjust_pc(drvdata);
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dev_emerg(dev, " EDPCSR: [<%px>] %pS\n", (void *)pc, (void *)pc);
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if (drvdata->edcidsr_present)
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dev_emerg(dev, " EDCIDSR: %08x\n", drvdata->edcidsr);
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if (drvdata->edvidsr_present)
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dev_emerg(dev, " EDVIDSR: %08x (State:%s Mode:%s Width:%dbits VMID:%x)\n",
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drvdata->edvidsr,
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drvdata->edvidsr & EDVIDSR_NS ?
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"Non-secure" : "Secure",
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drvdata->edvidsr & EDVIDSR_E3 ? "EL3" :
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(drvdata->edvidsr & EDVIDSR_E2 ?
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"EL2" : "EL1/0"),
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drvdata->edvidsr & EDVIDSR_HV ? 64 : 32,
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drvdata->edvidsr & (u32)EDVIDSR_VMID);
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}
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static void debug_init_arch_data(void *info)
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{
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struct debug_drvdata *drvdata = info;
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u32 mode, pcsr_offset;
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u32 eddevid, eddevid1;
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CS_UNLOCK(drvdata->base);
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/* Read device info */
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eddevid = readl_relaxed(drvdata->base + EDDEVID);
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eddevid1 = readl_relaxed(drvdata->base + EDDEVID1);
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CS_LOCK(drvdata->base);
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/* Parse implementation feature */
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mode = eddevid & EDDEVID_PCSAMPLE_MODE;
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pcsr_offset = eddevid1 & EDDEVID1_PCSR_OFFSET_MASK;
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drvdata->edpcsr_present = false;
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drvdata->edcidsr_present = false;
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drvdata->edvidsr_present = false;
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drvdata->pc_has_offset = false;
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switch (mode) {
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case EDDEVID_IMPL_FULL:
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drvdata->edvidsr_present = true;
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/* Fall through */
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case EDDEVID_IMPL_EDPCSR_EDCIDSR:
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drvdata->edcidsr_present = true;
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/* Fall through */
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case EDDEVID_IMPL_EDPCSR:
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/*
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* In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to
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* define if has the offset for PC sampling value; if read
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* back EDDEVID1.PCSROffset == 0x2, then this means the debug
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* module does not sample the instruction set state when
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* armv8 CPU in AArch32 state.
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*/
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drvdata->edpcsr_present =
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((IS_ENABLED(CONFIG_64BIT) && pcsr_offset != 0) ||
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(pcsr_offset != EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32));
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drvdata->pc_has_offset =
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(pcsr_offset == EDDEVID1_PCSR_OFFSET_INS_SET);
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break;
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default:
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break;
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}
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}
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/*
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* Dump out information on panic.
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*/
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static int debug_notifier_call(struct notifier_block *self,
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unsigned long v, void *p)
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{
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int cpu;
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struct debug_drvdata *drvdata;
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mutex_lock(&debug_lock);
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/* Bail out if the functionality is disabled */
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if (!debug_enable)
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goto skip_dump;
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pr_emerg("ARM external debug module:\n");
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for_each_possible_cpu(cpu) {
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drvdata = per_cpu(debug_drvdata, cpu);
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if (!drvdata)
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continue;
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dev_emerg(drvdata->dev, "CPU[%d]:\n", drvdata->cpu);
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debug_read_regs(drvdata);
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debug_dump_regs(drvdata);
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}
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skip_dump:
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mutex_unlock(&debug_lock);
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return 0;
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}
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static struct notifier_block debug_notifier = {
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.notifier_call = debug_notifier_call,
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};
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static int debug_enable_func(void)
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{
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struct debug_drvdata *drvdata;
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int cpu, ret = 0;
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cpumask_t mask;
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/*
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* Use cpumask to track which debug power domains have
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* been powered on and use it to handle failure case.
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*/
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cpumask_clear(&mask);
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for_each_possible_cpu(cpu) {
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drvdata = per_cpu(debug_drvdata, cpu);
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if (!drvdata)
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continue;
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ret = pm_runtime_get_sync(drvdata->dev);
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if (ret < 0)
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goto err;
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else
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cpumask_set_cpu(cpu, &mask);
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}
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return 0;
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err:
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/*
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* If pm_runtime_get_sync() has failed, need rollback on
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* all the other CPUs that have been enabled before that.
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*/
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for_each_cpu(cpu, &mask) {
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drvdata = per_cpu(debug_drvdata, cpu);
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pm_runtime_put_noidle(drvdata->dev);
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}
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return ret;
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}
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static int debug_disable_func(void)
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{
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struct debug_drvdata *drvdata;
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int cpu, ret, err = 0;
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/*
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* Disable debug power domains, records the error and keep
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* circling through all other CPUs when an error has been
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* encountered.
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*/
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for_each_possible_cpu(cpu) {
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drvdata = per_cpu(debug_drvdata, cpu);
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if (!drvdata)
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continue;
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ret = pm_runtime_put(drvdata->dev);
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if (ret < 0)
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err = ret;
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}
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return err;
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}
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static ssize_t debug_func_knob_write(struct file *f,
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const char __user *buf, size_t count, loff_t *ppos)
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{
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u8 val;
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int ret;
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ret = kstrtou8_from_user(buf, count, 2, &val);
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if (ret)
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return ret;
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mutex_lock(&debug_lock);
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if (val == debug_enable)
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goto out;
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if (val)
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ret = debug_enable_func();
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else
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ret = debug_disable_func();
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if (ret) {
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pr_err("%s: unable to %s debug function: %d\n",
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__func__, val ? "enable" : "disable", ret);
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goto err;
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}
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debug_enable = val;
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out:
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ret = count;
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err:
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mutex_unlock(&debug_lock);
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return ret;
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}
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static ssize_t debug_func_knob_read(struct file *f,
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char __user *ubuf, size_t count, loff_t *ppos)
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{
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ssize_t ret;
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char buf[3];
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mutex_lock(&debug_lock);
|
|
snprintf(buf, sizeof(buf), "%d\n", debug_enable);
|
|
mutex_unlock(&debug_lock);
|
|
|
|
ret = simple_read_from_buffer(ubuf, count, ppos, buf, sizeof(buf));
|
|
return ret;
|
|
}
|
|
|
|
static const struct file_operations debug_func_knob_fops = {
|
|
.open = simple_open,
|
|
.read = debug_func_knob_read,
|
|
.write = debug_func_knob_write,
|
|
};
|
|
|
|
static int debug_func_init(void)
|
|
{
|
|
struct dentry *file;
|
|
int ret;
|
|
|
|
/* Create debugfs node */
|
|
debug_debugfs_dir = debugfs_create_dir("coresight_cpu_debug", NULL);
|
|
if (!debug_debugfs_dir) {
|
|
pr_err("%s: unable to create debugfs directory\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
file = debugfs_create_file("enable", 0644, debug_debugfs_dir, NULL,
|
|
&debug_func_knob_fops);
|
|
if (!file) {
|
|
pr_err("%s: unable to create enable knob file\n", __func__);
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
/* Register function to be called for panic */
|
|
ret = atomic_notifier_chain_register(&panic_notifier_list,
|
|
&debug_notifier);
|
|
if (ret) {
|
|
pr_err("%s: unable to register notifier: %d\n",
|
|
__func__, ret);
|
|
goto err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
debugfs_remove_recursive(debug_debugfs_dir);
|
|
return ret;
|
|
}
|
|
|
|
static void debug_func_exit(void)
|
|
{
|
|
atomic_notifier_chain_unregister(&panic_notifier_list,
|
|
&debug_notifier);
|
|
debugfs_remove_recursive(debug_debugfs_dir);
|
|
}
|
|
|
|
static int debug_probe(struct amba_device *adev, const struct amba_id *id)
|
|
{
|
|
void __iomem *base;
|
|
struct device *dev = &adev->dev;
|
|
struct debug_drvdata *drvdata;
|
|
struct resource *res = &adev->res;
|
|
struct device_node *np = adev->dev.of_node;
|
|
int ret;
|
|
|
|
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
|
if (!drvdata)
|
|
return -ENOMEM;
|
|
|
|
drvdata->cpu = np ? of_coresight_get_cpu(np) : 0;
|
|
if (per_cpu(debug_drvdata, drvdata->cpu)) {
|
|
dev_err(dev, "CPU%d drvdata has already been initialized\n",
|
|
drvdata->cpu);
|
|
return -EBUSY;
|
|
}
|
|
|
|
drvdata->dev = &adev->dev;
|
|
amba_set_drvdata(adev, drvdata);
|
|
|
|
/* Validity for the resource is already checked by the AMBA core */
|
|
base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
drvdata->base = base;
|
|
|
|
get_online_cpus();
|
|
per_cpu(debug_drvdata, drvdata->cpu) = drvdata;
|
|
ret = smp_call_function_single(drvdata->cpu, debug_init_arch_data,
|
|
drvdata, 1);
|
|
put_online_cpus();
|
|
|
|
if (ret) {
|
|
dev_err(dev, "CPU%d debug arch init failed\n", drvdata->cpu);
|
|
goto err;
|
|
}
|
|
|
|
if (!drvdata->edpcsr_present) {
|
|
dev_err(dev, "CPU%d sample-based profiling isn't implemented\n",
|
|
drvdata->cpu);
|
|
ret = -ENXIO;
|
|
goto err;
|
|
}
|
|
|
|
if (!debug_count++) {
|
|
ret = debug_func_init();
|
|
if (ret)
|
|
goto err_func_init;
|
|
}
|
|
|
|
mutex_lock(&debug_lock);
|
|
/* Turn off debug power domain if debugging is disabled */
|
|
if (!debug_enable)
|
|
pm_runtime_put(dev);
|
|
mutex_unlock(&debug_lock);
|
|
|
|
dev_info(dev, "Coresight debug-CPU%d initialized\n", drvdata->cpu);
|
|
return 0;
|
|
|
|
err_func_init:
|
|
debug_count--;
|
|
err:
|
|
per_cpu(debug_drvdata, drvdata->cpu) = NULL;
|
|
return ret;
|
|
}
|
|
|
|
static int debug_remove(struct amba_device *adev)
|
|
{
|
|
struct device *dev = &adev->dev;
|
|
struct debug_drvdata *drvdata = amba_get_drvdata(adev);
|
|
|
|
per_cpu(debug_drvdata, drvdata->cpu) = NULL;
|
|
|
|
mutex_lock(&debug_lock);
|
|
/* Turn off debug power domain before rmmod the module */
|
|
if (debug_enable)
|
|
pm_runtime_put(dev);
|
|
mutex_unlock(&debug_lock);
|
|
|
|
if (!--debug_count)
|
|
debug_func_exit();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct amba_id debug_ids[] = {
|
|
{ /* Debug for Cortex-A53 */
|
|
.id = 0x000bbd03,
|
|
.mask = 0x000fffff,
|
|
},
|
|
{ /* Debug for Cortex-A57 */
|
|
.id = 0x000bbd07,
|
|
.mask = 0x000fffff,
|
|
},
|
|
{ /* Debug for Cortex-A72 */
|
|
.id = 0x000bbd08,
|
|
.mask = 0x000fffff,
|
|
},
|
|
{ 0, 0 },
|
|
};
|
|
|
|
static struct amba_driver debug_driver = {
|
|
.drv = {
|
|
.name = "coresight-cpu-debug",
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = debug_probe,
|
|
.remove = debug_remove,
|
|
.id_table = debug_ids,
|
|
};
|
|
|
|
module_amba_driver(debug_driver);
|
|
|
|
MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>");
|
|
MODULE_DESCRIPTION("ARM Coresight CPU Debug Driver");
|
|
MODULE_LICENSE("GPL");
|