Fabrice Gasnier e854a4ab38 counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update ... [ Upstream commit fd5ac974fc ] The ARR (auto reload register) and CMP (compare) registers are successively written. The status bits to check the update of these registers are polled together with regmap_read_poll_timeout(). The condition to end the loop may become true, even if one of the register isn't correctly updated. So ensure both status bits are set before clearing them. Fixes: d8958824cf ("iio: counter: Add support for STM32 LPTimer") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20221123133609.465614-1-fabrice.gasnier@foss.st.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-12-31 13:14:30 +01:00
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104-quad-8.c	…
Kconfig	…
Makefile	…
counter.c	…
ftm-quaddec.c	…
intel-qep.c	…
interrupt-cnt.c	…
microchip-tcb-capture.c	counter: microchip-tcb-capture: Handle Signal1 read and Synapse	2022-11-03 23:59:13 +09:00
stm32-lptimer-cnt.c	counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update	2022-12-31 13:14:30 +01:00
stm32-timer-cnt.c	…
ti-eqep.c	…