H. Nikolaus Schaller ecfaf0c42f w1:omap_hdq: fix regression ... Commit e93762bbf6 ("w1: masters: omap_hdq: add support for 1-wire mode") added a statement to clear the hdq_irqstatus flags in hdq_read_byte(). If the hdq reading process is scheduled slowly or interrupts are disabled for a while the hardware read activity might already be finished on entry of hdq_read_byte(). And hdq_isr() already has set the hdq_irqstatus to 0x6 (can be seen in debug mode) denoting that both, the TXCOMPLETE and RXCOMPLETE interrupts occurred in parallel. This means there is no need to wait and the hdq_read_byte() can just read the byte from the hdq controller. By resetting hdq_irqstatus to 0 the read process is forced to be always waiting again (because the if statement always succeeds) but the hardware will not issue another RXCOMPLETE interrupt. This results in a false timeout. After such a situation the hdq bus hangs. Link: http://lkml.kernel.org/r/b724765f87ad276a69625bc19806c8c8844c4590.1469513669.git.hns@goldelico.com Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Cc: Evgeniy Polyakov <zbr@ioremap.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: <stable@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>		2016-08-02 19:35:40 -04:00
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masters	w1:omap_hdq: fix regression	2016-08-02 19:35:40 -04:00
slaves	w1: add helper macro module_w1_family	2016-08-02 19:35:39 -04:00
Kconfig	…
Makefile	…
w1.c	w1: silence an uninitialized variable warning	2016-05-01 14:04:19 -07:00
w1.h	w1: add ability to set (SRAM) and store (EEPROM) configuration for temp sensors like DS18B20	2016-05-01 14:37:49 -07:00
w1_family.c	…
w1_family.h	w1: add helper macro module_w1_family	2016-08-02 19:35:39 -04:00
w1_int.c	…
w1_int.h	…
w1_io.c	…
w1_log.h	…
w1_netlink.c	…
w1_netlink.h	…