687 строки
15 KiB
C
687 строки
15 KiB
C
/*
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* Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
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*
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* Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
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*
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* VME support added by Sam Creasey
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*
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* TODO: modify this driver to support multiple Sun3 SCSI VME boards
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*
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* Adapted from mac_scsinew.c:
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*/
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/*
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* Generic Macintosh NCR5380 driver
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*
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* Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
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*
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* derived in part from:
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*/
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/*
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* Generic Generic NCR5380 driver
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*
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* Copyright 1995, Russell King
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*/
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include <asm/dvma.h>
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#include <scsi/scsi_host.h>
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#include "sun3_scsi.h"
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/* Definitions for the core NCR5380 driver. */
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#define REAL_DMA
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/* #define SUPPORT_TAGS */
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/* minimum number of bytes to do dma on */
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#define DMA_MIN_SIZE 129
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/* #define MAX_TAGS 32 */
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#define NCR5380_implementation_fields /* none */
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#define NCR5380_read(reg) sun3scsi_read(reg)
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#define NCR5380_write(reg, value) sun3scsi_write(reg, value)
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#define NCR5380_queue_command sun3scsi_queue_command
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#define NCR5380_bus_reset sun3scsi_bus_reset
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#define NCR5380_abort sun3scsi_abort
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#define NCR5380_show_info sun3scsi_show_info
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#define NCR5380_info sun3scsi_info
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#define NCR5380_dma_read_setup(instance, data, count) \
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sun3scsi_dma_setup(data, count, 0)
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#define NCR5380_dma_write_setup(instance, data, count) \
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sun3scsi_dma_setup(data, count, 1)
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#define NCR5380_dma_residual(instance) \
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sun3scsi_dma_residual(instance)
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#define NCR5380_dma_xfer_len(instance, cmd, phase) \
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sun3scsi_dma_xfer_len(cmd->SCp.this_residual, cmd, !((phase) & SR_IO))
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#define NCR5380_acquire_dma_irq(instance) (1)
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#define NCR5380_release_dma_irq(instance)
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#include "NCR5380.h"
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extern int sun3_map_test(unsigned long, char *);
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static int setup_can_queue = -1;
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module_param(setup_can_queue, int, 0);
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static int setup_cmd_per_lun = -1;
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module_param(setup_cmd_per_lun, int, 0);
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static int setup_sg_tablesize = -1;
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module_param(setup_sg_tablesize, int, 0);
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#ifdef SUPPORT_TAGS
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static int setup_use_tagged_queuing = -1;
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module_param(setup_use_tagged_queuing, int, 0);
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#endif
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static int setup_hostid = -1;
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module_param(setup_hostid, int, 0);
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/* #define RESET_BOOT */
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#define AFTER_RESET_DELAY (HZ/2)
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/* ms to wait after hitting dma regs */
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#define SUN3_DMA_DELAY 10
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/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
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#define SUN3_DVMA_BUFSIZE 0xe000
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static struct scsi_cmnd *sun3_dma_setup_done;
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static unsigned char *sun3_scsi_regp;
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static volatile struct sun3_dma_regs *dregs;
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static struct sun3_udc_regs *udc_regs;
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static unsigned char *sun3_dma_orig_addr = NULL;
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static unsigned long sun3_dma_orig_count = 0;
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static int sun3_dma_active = 0;
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static unsigned long last_residual = 0;
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static struct Scsi_Host *default_instance;
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/*
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* NCR 5380 register access functions
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*/
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static inline unsigned char sun3scsi_read(int reg)
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{
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return in_8(sun3_scsi_regp + reg);
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}
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static inline void sun3scsi_write(int reg, int value)
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{
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out_8(sun3_scsi_regp + reg, value);
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}
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#ifndef SUN3_SCSI_VME
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/* dma controller register access functions */
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static inline unsigned short sun3_udc_read(unsigned char reg)
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{
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unsigned short ret;
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dregs->udc_addr = UDC_CSR;
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udelay(SUN3_DMA_DELAY);
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ret = dregs->udc_data;
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udelay(SUN3_DMA_DELAY);
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return ret;
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}
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static inline void sun3_udc_write(unsigned short val, unsigned char reg)
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{
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dregs->udc_addr = reg;
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udelay(SUN3_DMA_DELAY);
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dregs->udc_data = val;
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udelay(SUN3_DMA_DELAY);
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}
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#endif
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#ifdef RESET_BOOT
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static void sun3_scsi_reset_boot(struct Scsi_Host *instance)
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{
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unsigned long end;
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/*
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* Do a SCSI reset to clean up the bus during initialization. No
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* messing with the queues, interrupts, or locks necessary here.
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*/
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printk( "Sun3 SCSI: resetting the SCSI bus..." );
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/* switch off SCSI IRQ - catch an interrupt without IRQ bit set else */
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// sun3_disable_irq( IRQ_SUN3_SCSI );
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/* get in phase */
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NCR5380_write( TARGET_COMMAND_REG,
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PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
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/* assert RST */
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NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
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/* The min. reset hold time is 25us, so 40us should be enough */
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udelay( 50 );
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/* reset RST and interrupt */
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NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
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NCR5380_read( RESET_PARITY_INTERRUPT_REG );
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for( end = jiffies + AFTER_RESET_DELAY; time_before(jiffies, end); )
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barrier();
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/* switch on SCSI IRQ again */
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// sun3_enable_irq( IRQ_SUN3_SCSI );
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printk( " done\n" );
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}
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#endif
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// safe bits for the CSR
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#define CSR_GOOD 0x060f
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static irqreturn_t scsi_sun3_intr(int irq, void *dummy)
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{
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unsigned short csr = dregs->csr;
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int handled = 0;
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#ifdef SUN3_SCSI_VME
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dregs->csr &= ~CSR_DMA_ENABLE;
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#endif
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if(csr & ~CSR_GOOD) {
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if(csr & CSR_DMA_BUSERR) {
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printk("scsi%d: bus error in dma\n", default_instance->host_no);
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}
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if(csr & CSR_DMA_CONFLICT) {
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printk("scsi%d: dma conflict\n", default_instance->host_no);
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}
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handled = 1;
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}
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if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
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NCR5380_intr(irq, dummy);
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handled = 1;
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}
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return IRQ_RETVAL(handled);
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}
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/*
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* Debug stuff - to be called on NMI, or sysrq key. Use at your own risk;
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* reentering NCR5380_print_status seems to have ugly side effects
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*/
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/* this doesn't seem to get used at all -- sam */
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#if 0
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void sun3_sun3_debug (void)
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{
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unsigned long flags;
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if (default_instance) {
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local_irq_save(flags);
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NCR5380_print_status(default_instance);
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local_irq_restore(flags);
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}
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}
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#endif
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/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
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static unsigned long sun3scsi_dma_setup(void *data, unsigned long count, int write_flag)
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{
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void *addr;
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if(sun3_dma_orig_addr != NULL)
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dvma_unmap(sun3_dma_orig_addr);
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#ifdef SUN3_SCSI_VME
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addr = (void *)dvma_map_vme((unsigned long) data, count);
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#else
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addr = (void *)dvma_map((unsigned long) data, count);
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#endif
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sun3_dma_orig_addr = addr;
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sun3_dma_orig_count = count;
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#ifndef SUN3_SCSI_VME
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dregs->fifo_count = 0;
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sun3_udc_write(UDC_RESET, UDC_CSR);
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/* reset fifo */
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dregs->csr &= ~CSR_FIFO;
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dregs->csr |= CSR_FIFO;
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#endif
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/* set direction */
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if(write_flag)
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dregs->csr |= CSR_SEND;
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else
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dregs->csr &= ~CSR_SEND;
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#ifdef SUN3_SCSI_VME
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dregs->csr |= CSR_PACK_ENABLE;
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dregs->dma_addr_hi = ((unsigned long)addr >> 16);
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dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
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dregs->dma_count_hi = 0;
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dregs->dma_count_lo = 0;
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dregs->fifo_count_hi = 0;
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dregs->fifo_count = 0;
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#else
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/* byte count for fifo */
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dregs->fifo_count = count;
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sun3_udc_write(UDC_RESET, UDC_CSR);
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/* reset fifo */
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dregs->csr &= ~CSR_FIFO;
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dregs->csr |= CSR_FIFO;
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if(dregs->fifo_count != count) {
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printk("scsi%d: fifo_mismatch %04x not %04x\n",
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default_instance->host_no, dregs->fifo_count,
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(unsigned int) count);
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NCR5380_dprint(NDEBUG_DMA, default_instance);
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}
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/* setup udc */
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udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
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udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
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udc_regs->count = count/2; /* count in words */
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udc_regs->mode_hi = UDC_MODE_HIWORD;
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if(write_flag) {
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if(count & 1)
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udc_regs->count++;
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udc_regs->mode_lo = UDC_MODE_LSEND;
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udc_regs->rsel = UDC_RSEL_SEND;
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} else {
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udc_regs->mode_lo = UDC_MODE_LRECV;
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udc_regs->rsel = UDC_RSEL_RECV;
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}
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/* announce location of regs block */
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sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
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UDC_CHN_HI);
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sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
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/* set dma master on */
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sun3_udc_write(0xd, UDC_MODE);
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/* interrupt enable */
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sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
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#endif
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return count;
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}
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#ifndef SUN3_SCSI_VME
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static inline unsigned long sun3scsi_dma_count(struct Scsi_Host *instance)
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{
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unsigned short resid;
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dregs->udc_addr = 0x32;
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udelay(SUN3_DMA_DELAY);
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resid = dregs->udc_data;
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udelay(SUN3_DMA_DELAY);
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resid *= 2;
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return (unsigned long) resid;
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}
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#endif
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static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance)
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{
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return last_residual;
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}
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static inline unsigned long sun3scsi_dma_xfer_len(unsigned long wanted,
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struct scsi_cmnd *cmd,
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int write_flag)
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{
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if (cmd->request->cmd_type == REQ_TYPE_FS)
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return wanted;
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else
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return 0;
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}
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static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
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{
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#ifdef SUN3_SCSI_VME
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unsigned short csr;
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csr = dregs->csr;
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dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
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dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
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dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
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dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
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/* if(!(csr & CSR_DMA_ENABLE))
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* dregs->csr |= CSR_DMA_ENABLE;
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*/
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#else
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sun3_udc_write(UDC_CHN_START, UDC_CSR);
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#endif
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return 0;
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}
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/* clean up after our dma is done */
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static int sun3scsi_dma_finish(int write_flag)
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{
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unsigned short __maybe_unused count;
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unsigned short fifo;
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int ret = 0;
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sun3_dma_active = 0;
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#ifdef SUN3_SCSI_VME
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dregs->csr &= ~CSR_DMA_ENABLE;
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fifo = dregs->fifo_count;
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if (write_flag) {
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if ((fifo > 0) && (fifo < sun3_dma_orig_count))
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fifo++;
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}
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last_residual = fifo;
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/* empty bytes from the fifo which didn't make it */
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if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
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unsigned char *vaddr;
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vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
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vaddr += (sun3_dma_orig_count - fifo);
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vaddr--;
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switch (dregs->csr & CSR_LEFT) {
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case CSR_LEFT_3:
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*vaddr = (dregs->bpack_lo & 0xff00) >> 8;
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vaddr--;
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case CSR_LEFT_2:
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*vaddr = (dregs->bpack_hi & 0x00ff);
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vaddr--;
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case CSR_LEFT_1:
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*vaddr = (dregs->bpack_hi & 0xff00) >> 8;
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break;
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}
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}
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#else
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// check to empty the fifo on a read
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if(!write_flag) {
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int tmo = 20000; /* .2 sec */
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while(1) {
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if(dregs->csr & CSR_FIFO_EMPTY)
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break;
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if(--tmo <= 0) {
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printk("sun3scsi: fifo failed to empty!\n");
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return 1;
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}
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udelay(10);
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}
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}
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count = sun3scsi_dma_count(default_instance);
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fifo = dregs->fifo_count;
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last_residual = fifo;
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/* empty bytes from the fifo which didn't make it */
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if((!write_flag) && (count - fifo) == 2) {
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unsigned short data;
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unsigned char *vaddr;
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data = dregs->fifo_data;
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vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
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vaddr += (sun3_dma_orig_count - fifo);
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vaddr[-2] = (data & 0xff00) >> 8;
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vaddr[-1] = (data & 0xff);
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}
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#endif
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dvma_unmap(sun3_dma_orig_addr);
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sun3_dma_orig_addr = NULL;
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#ifdef SUN3_SCSI_VME
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dregs->dma_addr_hi = 0;
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dregs->dma_addr_lo = 0;
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dregs->dma_count_hi = 0;
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dregs->dma_count_lo = 0;
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dregs->fifo_count = 0;
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dregs->fifo_count_hi = 0;
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dregs->csr &= ~CSR_SEND;
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/* dregs->csr |= CSR_DMA_ENABLE; */
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#else
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sun3_udc_write(UDC_RESET, UDC_CSR);
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dregs->fifo_count = 0;
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dregs->csr &= ~CSR_SEND;
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/* reset fifo */
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dregs->csr &= ~CSR_FIFO;
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dregs->csr |= CSR_FIFO;
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#endif
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sun3_dma_setup_done = NULL;
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return ret;
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}
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#include "atari_NCR5380.c"
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#ifdef SUN3_SCSI_VME
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#define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
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#define DRV_MODULE_NAME "sun3_scsi_vme"
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#else
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#define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
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#define DRV_MODULE_NAME "sun3_scsi"
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#endif
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#define PFX DRV_MODULE_NAME ": "
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static struct scsi_host_template sun3_scsi_template = {
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.module = THIS_MODULE,
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.proc_name = DRV_MODULE_NAME,
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.show_info = sun3scsi_show_info,
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.name = SUN3_SCSI_NAME,
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.info = sun3scsi_info,
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.queuecommand = sun3scsi_queue_command,
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.eh_abort_handler = sun3scsi_abort,
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.eh_bus_reset_handler = sun3scsi_bus_reset,
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.can_queue = 16,
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.this_id = 7,
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.sg_tablesize = SG_NONE,
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.cmd_per_lun = 2,
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.use_clustering = DISABLE_CLUSTERING
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};
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static int __init sun3_scsi_probe(struct platform_device *pdev)
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{
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struct Scsi_Host *instance;
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int error;
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struct resource *irq, *mem;
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|
unsigned char *ioaddr;
|
|
int host_flags = 0;
|
|
#ifdef SUN3_SCSI_VME
|
|
int i;
|
|
#endif
|
|
|
|
if (setup_can_queue > 0)
|
|
sun3_scsi_template.can_queue = setup_can_queue;
|
|
if (setup_cmd_per_lun > 0)
|
|
sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
|
|
if (setup_sg_tablesize >= 0)
|
|
sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
|
|
if (setup_hostid >= 0)
|
|
sun3_scsi_template.this_id = setup_hostid & 7;
|
|
|
|
#ifdef SUN3_SCSI_VME
|
|
ioaddr = NULL;
|
|
for (i = 0; i < 2; i++) {
|
|
unsigned char x;
|
|
|
|
irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
|
if (!irq || !mem)
|
|
break;
|
|
|
|
ioaddr = sun3_ioremap(mem->start, resource_size(mem),
|
|
SUN3_PAGE_TYPE_VME16);
|
|
dregs = (struct sun3_dma_regs *)(ioaddr + 8);
|
|
|
|
if (sun3_map_test((unsigned long)dregs, &x)) {
|
|
unsigned short oldcsr;
|
|
|
|
oldcsr = dregs->csr;
|
|
dregs->csr = 0;
|
|
udelay(SUN3_DMA_DELAY);
|
|
if (dregs->csr == 0x1400)
|
|
break;
|
|
|
|
dregs->csr = oldcsr;
|
|
}
|
|
|
|
iounmap(ioaddr);
|
|
ioaddr = NULL;
|
|
}
|
|
if (!ioaddr)
|
|
return -ENODEV;
|
|
#else
|
|
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!irq || !mem)
|
|
return -ENODEV;
|
|
|
|
ioaddr = ioremap(mem->start, resource_size(mem));
|
|
dregs = (struct sun3_dma_regs *)(ioaddr + 8);
|
|
|
|
udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
|
|
if (!udc_regs) {
|
|
pr_err(PFX "couldn't allocate DVMA memory!\n");
|
|
iounmap(ioaddr);
|
|
return -ENOMEM;
|
|
}
|
|
#endif
|
|
|
|
sun3_scsi_regp = ioaddr;
|
|
|
|
instance = scsi_host_alloc(&sun3_scsi_template,
|
|
sizeof(struct NCR5380_hostdata));
|
|
if (!instance) {
|
|
error = -ENOMEM;
|
|
goto fail_alloc;
|
|
}
|
|
default_instance = instance;
|
|
|
|
instance->io_port = (unsigned long)ioaddr;
|
|
instance->irq = irq->start;
|
|
|
|
#ifdef SUPPORT_TAGS
|
|
host_flags |= setup_use_tagged_queuing > 0 ? FLAG_TAGGED_QUEUING : 0;
|
|
#endif
|
|
|
|
NCR5380_init(instance, host_flags);
|
|
|
|
error = request_irq(instance->irq, scsi_sun3_intr, 0,
|
|
"NCR5380", instance);
|
|
if (error) {
|
|
#ifdef REAL_DMA
|
|
pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
|
|
instance->host_no, instance->irq);
|
|
goto fail_irq;
|
|
#else
|
|
pr_warn(PFX "scsi%d: IRQ %d not free, interrupts disabled\n",
|
|
instance->host_no, instance->irq);
|
|
instance->irq = NO_IRQ;
|
|
#endif
|
|
}
|
|
|
|
dregs->csr = 0;
|
|
udelay(SUN3_DMA_DELAY);
|
|
dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
|
|
udelay(SUN3_DMA_DELAY);
|
|
dregs->fifo_count = 0;
|
|
#ifdef SUN3_SCSI_VME
|
|
dregs->fifo_count_hi = 0;
|
|
dregs->dma_addr_hi = 0;
|
|
dregs->dma_addr_lo = 0;
|
|
dregs->dma_count_hi = 0;
|
|
dregs->dma_count_lo = 0;
|
|
|
|
dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
|
|
#endif
|
|
|
|
#ifdef RESET_BOOT
|
|
sun3_scsi_reset_boot(instance);
|
|
#endif
|
|
|
|
error = scsi_add_host(instance, NULL);
|
|
if (error)
|
|
goto fail_host;
|
|
|
|
platform_set_drvdata(pdev, instance);
|
|
|
|
scsi_scan_host(instance);
|
|
return 0;
|
|
|
|
fail_host:
|
|
if (instance->irq != NO_IRQ)
|
|
free_irq(instance->irq, instance);
|
|
fail_irq:
|
|
NCR5380_exit(instance);
|
|
scsi_host_put(instance);
|
|
fail_alloc:
|
|
if (udc_regs)
|
|
dvma_free(udc_regs);
|
|
iounmap(sun3_scsi_regp);
|
|
return error;
|
|
}
|
|
|
|
static int __exit sun3_scsi_remove(struct platform_device *pdev)
|
|
{
|
|
struct Scsi_Host *instance = platform_get_drvdata(pdev);
|
|
|
|
scsi_remove_host(instance);
|
|
if (instance->irq != NO_IRQ)
|
|
free_irq(instance->irq, instance);
|
|
NCR5380_exit(instance);
|
|
scsi_host_put(instance);
|
|
if (udc_regs)
|
|
dvma_free(udc_regs);
|
|
iounmap(sun3_scsi_regp);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sun3_scsi_driver = {
|
|
.remove = __exit_p(sun3_scsi_remove),
|
|
.driver = {
|
|
.name = DRV_MODULE_NAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
|
|
|
|
MODULE_ALIAS("platform:" DRV_MODULE_NAME);
|
|
MODULE_LICENSE("GPL");
|