401 строка
10 KiB
C
401 строка
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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*/
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/*
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* Someday its supposed to make use of the WT DMA engine
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* for a Wavetable synthesizer.
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*/
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#include "au88x0.h"
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#include "au88x0_wt.h"
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static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en);
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static void vortex_connection_adb_mixin(vortex_t * vortex, int en,
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unsigned char channel,
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unsigned char source,
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unsigned char mixin);
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static void vortex_connection_mixin_mix(vortex_t * vortex, int en,
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unsigned char mixin,
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unsigned char mix, int a);
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static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j);
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static int vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt,
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u32 val);
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/* WT */
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/* Put 2 WT channels together for one stereo interlaced channel. */
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static void vortex_wt_setstereo(vortex_t * vortex, u32 wt, u32 stereo)
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{
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int temp;
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//temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2));
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temp = hwread(vortex->mmio, WT_STEREO(wt));
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temp = (temp & 0xfe) | (stereo & 1);
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//hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp);
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hwwrite(vortex->mmio, WT_STEREO(wt), temp);
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}
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/* Join to mixdown route. */
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static void vortex_wt_setdsout(vortex_t * vortex, u32 wt, int en)
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{
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int temp;
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/* There is one DSREG register for each bank (32 voices each). */
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temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0));
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if (en)
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temp |= (1 << (wt & 0x1f));
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else
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temp &= ~(1 << (wt & 0x1f));
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hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp);
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}
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/* Setup WT route. */
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static int vortex_wt_allocroute(vortex_t * vortex, int wt, int nr_ch)
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{
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wt_voice_t *voice = &(vortex->wt_voice[wt]);
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int temp;
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//FIXME: WT audio routing.
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if (nr_ch) {
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vortex_fifo_wtinitialize(vortex, wt, 1);
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vortex_fifo_setwtvalid(vortex, wt, 1);
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vortex_wt_setstereo(vortex, wt, nr_ch - 1);
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} else
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vortex_fifo_setwtvalid(vortex, wt, 0);
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/* Set mixdown mode. */
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vortex_wt_setdsout(vortex, wt, 1);
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/* Set other parameter registers. */
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hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000);
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//hwwrite(vortex->mmio, WT_GMODE(0), 0xffffffff);
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#ifdef CHIP_AU8830
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hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000);
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//hwwrite(vortex->mmio, WT_GMODE(1), 0xffffffff);
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#endif
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hwwrite(vortex->mmio, WT_PARM(wt, 0), 0);
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hwwrite(vortex->mmio, WT_PARM(wt, 1), 0);
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hwwrite(vortex->mmio, WT_PARM(wt, 2), 0);
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temp = hwread(vortex->mmio, WT_PARM(wt, 3));
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dev_dbg(vortex->card->dev, "WT PARM3: %x\n", temp);
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//hwwrite(vortex->mmio, WT_PARM(wt, 3), temp);
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hwwrite(vortex->mmio, WT_DELAY(wt, 0), 0);
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hwwrite(vortex->mmio, WT_DELAY(wt, 1), 0);
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hwwrite(vortex->mmio, WT_DELAY(wt, 2), 0);
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hwwrite(vortex->mmio, WT_DELAY(wt, 3), 0);
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dev_dbg(vortex->card->dev, "WT GMODE: %x\n",
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hwread(vortex->mmio, WT_GMODE(wt)));
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hwwrite(vortex->mmio, WT_PARM(wt, 2), 0xffffffff);
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hwwrite(vortex->mmio, WT_PARM(wt, 3), 0xcff1c810);
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voice->parm0 = voice->parm1 = 0xcfb23e2f;
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hwwrite(vortex->mmio, WT_PARM(wt, 0), voice->parm0);
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hwwrite(vortex->mmio, WT_PARM(wt, 1), voice->parm1);
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dev_dbg(vortex->card->dev, "WT GMODE 2 : %x\n",
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hwread(vortex->mmio, WT_GMODE(wt)));
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return 0;
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}
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static void vortex_wt_connect(vortex_t * vortex, int en)
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{
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int i, ii, mix;
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#define NR_WTROUTES 6
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#ifdef CHIP_AU8830
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#define NR_WTBLOCKS 2
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#else
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#define NR_WTBLOCKS 1
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#endif
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for (i = 0; i < NR_WTBLOCKS; i++) {
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for (ii = 0; ii < NR_WTROUTES; ii++) {
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mix =
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vortex_adb_checkinout(vortex,
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vortex->fixed_res, en,
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VORTEX_RESOURCE_MIXIN);
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vortex->mixwt[(i * NR_WTROUTES) + ii] = mix;
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vortex_route(vortex, en, 0x11,
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ADB_WTOUT(i, ii + 0x20), ADB_MIXIN(mix));
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vortex_connection_mixin_mix(vortex, en, mix,
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vortex->mixplayb[ii % 2], 0);
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if (VORTEX_IS_QUAD(vortex))
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vortex_connection_mixin_mix(vortex, en,
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mix,
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vortex->mixplayb[2 +
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(ii % 2)], 0);
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}
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}
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for (i = 0; i < NR_WT; i++) {
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hwwrite(vortex->mmio, WT_RUN(i), 1);
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}
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}
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/* Read WT Register */
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#if 0
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static int vortex_wt_GetReg(vortex_t * vortex, char reg, int wt)
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{
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//int eax, esi;
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if (reg == 4) {
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return hwread(vortex->mmio, WT_PARM(wt, 3));
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}
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if (reg == 7) {
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return hwread(vortex->mmio, WT_GMODE(wt));
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}
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return 0;
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}
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/* WT hardware abstraction layer generic register interface. */
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static int
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vortex_wt_SetReg2(vortex_t * vortex, unsigned char reg, int wt,
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u16 val)
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{
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/*
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int eax, edx;
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if (wt >= NR_WT) // 0x40 -> NR_WT
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return 0;
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if ((reg - 0x20) > 0) {
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if ((reg - 0x21) != 0)
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return 0;
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eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x208; // param 2
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} else {
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eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x20a; // param 3
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}
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hwwrite(vortex->mmio, eax, c);
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*/
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return 1;
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}
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/*public: static void __thiscall CWTHal::SetReg(unsigned char,int,unsigned long) */
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#endif
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static int
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vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt,
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u32 val)
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{
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int ecx;
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if ((reg == 5) || ((reg >= 7) && (reg <= 10)) || (reg == 0xc)) {
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if (wt >= (NR_WT / NR_WT_PB)) {
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dev_warn(vortex->card->dev,
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"WT SetReg: bank out of range. reg=0x%x, wt=%d\n",
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reg, wt);
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return 0;
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}
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} else {
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if (wt >= NR_WT) {
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dev_err(vortex->card->dev,
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"WT SetReg: voice out of range\n");
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return 0;
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}
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}
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if (reg > 0xc)
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return 0;
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switch (reg) {
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/* Voice specific parameters */
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case 0: /* running */
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/*
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pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
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WT_RUN(wt), (int)val);
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*/
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hwwrite(vortex->mmio, WT_RUN(wt), val);
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return 0xc;
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case 1: /* param 0 */
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/*
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pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
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WT_PARM(wt,0), (int)val);
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*/
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hwwrite(vortex->mmio, WT_PARM(wt, 0), val);
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return 0xc;
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case 2: /* param 1 */
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/*
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pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
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WT_PARM(wt,1), (int)val);
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*/
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hwwrite(vortex->mmio, WT_PARM(wt, 1), val);
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return 0xc;
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case 3: /* param 2 */
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/*
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pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
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WT_PARM(wt,2), (int)val);
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*/
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hwwrite(vortex->mmio, WT_PARM(wt, 2), val);
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return 0xc;
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case 4: /* param 3 */
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/*
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pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
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WT_PARM(wt,3), (int)val);
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*/
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hwwrite(vortex->mmio, WT_PARM(wt, 3), val);
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return 0xc;
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case 6: /* mute */
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/*
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pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
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WT_MUTE(wt), (int)val);
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*/
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hwwrite(vortex->mmio, WT_MUTE(wt), val);
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return 0xc;
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case 0xb:
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/* delay */
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/*
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pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
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WT_DELAY(wt,0), (int)val);
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*/
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hwwrite(vortex->mmio, WT_DELAY(wt, 3), val);
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hwwrite(vortex->mmio, WT_DELAY(wt, 2), val);
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hwwrite(vortex->mmio, WT_DELAY(wt, 1), val);
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hwwrite(vortex->mmio, WT_DELAY(wt, 0), val);
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return 0xc;
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/* Global WT block parameters */
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case 5: /* sramp */
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ecx = WT_SRAMP(wt);
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break;
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case 8: /* aramp */
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ecx = WT_ARAMP(wt);
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break;
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case 9: /* mramp */
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ecx = WT_MRAMP(wt);
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break;
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case 0xa: /* ctrl */
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ecx = WT_CTRL(wt);
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break;
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case 0xc: /* ds_reg */
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ecx = WT_DSREG(wt);
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break;
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default:
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return 0;
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}
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/*
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pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", ecx, (int)val);
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*/
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hwwrite(vortex->mmio, ecx, val);
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return 1;
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}
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static void vortex_wt_init(vortex_t * vortex)
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{
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u32 var4, var8, varc, var10 = 0, edi;
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var10 &= 0xFFFFFFE3;
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var10 |= 0x22;
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var10 &= 0xFFFFFEBF;
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var10 |= 0x80;
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var10 |= 0x200;
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var10 &= 0xfffffffe;
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var10 &= 0xfffffbff;
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var10 |= 0x1800;
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// var10 = 0x1AA2
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var4 = 0x10000000;
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varc = 0x00830000;
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var8 = 0x00830000;
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/* Init Bank registers. */
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for (edi = 0; edi < (NR_WT / NR_WT_PB); edi++) {
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vortex_wt_SetReg(vortex, 0xc, edi, 0); /* ds_reg */
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vortex_wt_SetReg(vortex, 0xa, edi, var10); /* ctrl */
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vortex_wt_SetReg(vortex, 0x9, edi, var4); /* mramp */
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vortex_wt_SetReg(vortex, 0x8, edi, varc); /* aramp */
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vortex_wt_SetReg(vortex, 0x5, edi, var8); /* sramp */
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}
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/* Init Voice registers. */
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for (edi = 0; edi < NR_WT; edi++) {
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vortex_wt_SetReg(vortex, 0x4, edi, 0); /* param 3 0x20c */
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vortex_wt_SetReg(vortex, 0x3, edi, 0); /* param 2 0x208 */
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vortex_wt_SetReg(vortex, 0x2, edi, 0); /* param 1 0x204 */
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vortex_wt_SetReg(vortex, 0x1, edi, 0); /* param 0 0x200 */
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vortex_wt_SetReg(vortex, 0xb, edi, 0); /* delay 0x400 - 0x40c */
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}
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var10 |= 1;
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for (edi = 0; edi < (NR_WT / NR_WT_PB); edi++)
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vortex_wt_SetReg(vortex, 0xa, edi, var10); /* ctrl */
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}
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/* Extract of CAdbTopology::SetVolume(struct _ASPVOLUME *) */
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#if 0
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static void vortex_wt_SetVolume(vortex_t * vortex, int wt, int vol[])
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{
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wt_voice_t *voice = &(vortex->wt_voice[wt]);
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int ecx = vol[1], eax = vol[0];
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/* This is pure guess */
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voice->parm0 &= 0xff00ffff;
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voice->parm0 |= (vol[0] & 0xff) << 0x10;
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voice->parm1 &= 0xff00ffff;
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voice->parm1 |= (vol[1] & 0xff) << 0x10;
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/* This is real */
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hwwrite(vortex, WT_PARM(wt, 0), voice->parm0);
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hwwrite(vortex, WT_PARM(wt, 1), voice->parm0);
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if (voice->this_1D0 & 4) {
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eax >>= 8;
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ecx = eax;
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if (ecx < 0x80)
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ecx = 0x7f;
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voice->parm3 &= 0xFFFFC07F;
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voice->parm3 |= (ecx & 0x7f) << 7;
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voice->parm3 &= 0xFFFFFF80;
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voice->parm3 |= (eax & 0x7f);
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} else {
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voice->parm3 &= 0xFFE03FFF;
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voice->parm3 |= (eax & 0xFE00) << 5;
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}
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hwwrite(vortex, WT_PARM(wt, 3), voice->parm3);
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}
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/* Extract of CAdbTopology::SetFrequency(unsigned long arg_0) */
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static void vortex_wt_SetFrequency(vortex_t * vortex, int wt, unsigned int sr)
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{
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wt_voice_t *voice = &(vortex->wt_voice[wt]);
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u32 eax, edx;
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//FIXME: 64 bit operation.
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eax = ((sr << 0xf) * 0x57619F1) & 0xffffffff;
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edx = (((sr << 0xf) * 0x57619F1)) >> 0x20;
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edx >>= 0xa;
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edx <<= 1;
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if (edx) {
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if (edx & 0x0FFF80000)
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eax = 0x7fff;
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else {
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edx <<= 0xd;
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eax = 7;
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while ((edx & 0x80000000) == 0) {
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edx <<= 1;
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eax--;
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if (eax == 0)
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break;
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}
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if (eax)
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edx <<= 1;
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eax <<= 0xc;
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edx >>= 0x14;
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eax |= edx;
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}
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} else
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eax = 0;
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voice->parm0 &= 0xffff0001;
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voice->parm0 |= (eax & 0x7fff) << 1;
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voice->parm1 = voice->parm0 | 1;
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// Wt: this_1D4
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//AuWt::WriteReg((ulong)(this_1DC<<4)+0x200, (ulong)this_1E4);
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//AuWt::WriteReg((ulong)(this_1DC<<4)+0x204, (ulong)this_1E8);
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hwwrite(vortex->mmio, WT_PARM(wt, 0), voice->parm0);
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hwwrite(vortex->mmio, WT_PARM(wt, 1), voice->parm1);
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}
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#endif
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/* End of File */
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