990 строки
25 KiB
C
990 строки
25 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* ***************************************************************************
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* Marvell Armada-3700 Serial Driver
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* Author: Wilson Ding <dingwei@marvell.com>
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* Copyright (C) 2015 Marvell International Ltd.
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* ***************************************************************************
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*/
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#include <linux/clk.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/slab.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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/* Register Map */
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#define UART_STD_RBR 0x00
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#define UART_EXT_RBR 0x18
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#define UART_STD_TSH 0x04
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#define UART_EXT_TSH 0x1C
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#define UART_STD_CTRL1 0x08
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#define UART_EXT_CTRL1 0x04
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#define CTRL_SOFT_RST BIT(31)
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#define CTRL_TXFIFO_RST BIT(15)
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#define CTRL_RXFIFO_RST BIT(14)
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#define CTRL_SND_BRK_SEQ BIT(11)
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#define CTRL_BRK_DET_INT BIT(3)
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#define CTRL_FRM_ERR_INT BIT(2)
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#define CTRL_PAR_ERR_INT BIT(1)
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#define CTRL_OVR_ERR_INT BIT(0)
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#define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
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CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
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#define UART_STD_CTRL2 UART_STD_CTRL1
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#define UART_EXT_CTRL2 0x20
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#define CTRL_STD_TX_RDY_INT BIT(5)
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#define CTRL_EXT_TX_RDY_INT BIT(6)
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#define CTRL_STD_RX_RDY_INT BIT(4)
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#define CTRL_EXT_RX_RDY_INT BIT(5)
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#define UART_STAT 0x0C
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#define STAT_TX_FIFO_EMP BIT(13)
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#define STAT_TX_FIFO_FUL BIT(11)
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#define STAT_TX_EMP BIT(6)
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#define STAT_STD_TX_RDY BIT(5)
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#define STAT_EXT_TX_RDY BIT(15)
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#define STAT_STD_RX_RDY BIT(4)
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#define STAT_EXT_RX_RDY BIT(14)
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#define STAT_BRK_DET BIT(3)
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#define STAT_FRM_ERR BIT(2)
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#define STAT_PAR_ERR BIT(1)
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#define STAT_OVR_ERR BIT(0)
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#define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR \
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| STAT_PAR_ERR | STAT_OVR_ERR)
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#define UART_BRDV 0x10
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#define BRDV_BAUD_MASK 0x3FF
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#define UART_OSAMP 0x14
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#define OSAMP_DEFAULT_DIVISOR 16
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#define OSAMP_DIVISORS_MASK 0x3F3F3F3F
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#define MVEBU_NR_UARTS 2
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#define MVEBU_UART_TYPE "mvebu-uart"
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#define DRIVER_NAME "mvebu_serial"
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enum {
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/* Either there is only one summed IRQ... */
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UART_IRQ_SUM = 0,
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/* ...or there are two separate IRQ for RX and TX */
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UART_RX_IRQ = 0,
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UART_TX_IRQ,
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UART_IRQ_COUNT
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};
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/* Diverging register offsets */
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struct uart_regs_layout {
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unsigned int rbr;
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unsigned int tsh;
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unsigned int ctrl;
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unsigned int intr;
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};
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/* Diverging flags */
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struct uart_flags {
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unsigned int ctrl_tx_rdy_int;
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unsigned int ctrl_rx_rdy_int;
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unsigned int stat_tx_rdy;
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unsigned int stat_rx_rdy;
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};
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/* Driver data, a structure for each UART port */
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struct mvebu_uart_driver_data {
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bool is_ext;
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struct uart_regs_layout regs;
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struct uart_flags flags;
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};
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/* Saved registers during suspend */
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struct mvebu_uart_pm_regs {
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unsigned int rbr;
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unsigned int tsh;
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unsigned int ctrl;
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unsigned int intr;
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unsigned int stat;
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unsigned int brdv;
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unsigned int osamp;
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};
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/* MVEBU UART driver structure */
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struct mvebu_uart {
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struct uart_port *port;
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struct clk *clk;
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int irq[UART_IRQ_COUNT];
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struct mvebu_uart_driver_data *data;
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#if defined(CONFIG_PM)
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struct mvebu_uart_pm_regs pm_regs;
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#endif /* CONFIG_PM */
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};
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static struct mvebu_uart *to_mvuart(struct uart_port *port)
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{
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return (struct mvebu_uart *)port->private_data;
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}
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#define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
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#define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
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#define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
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#define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
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#define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
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#define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
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#define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
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#define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
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#define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
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static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
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/* Core UART Driver Operations */
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static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
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{
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unsigned long flags;
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unsigned int st;
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spin_lock_irqsave(&port->lock, flags);
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st = readl(port->membase + UART_STAT);
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spin_unlock_irqrestore(&port->lock, flags);
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return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0;
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}
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static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
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}
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static void mvebu_uart_set_mctrl(struct uart_port *port,
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unsigned int mctrl)
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{
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/*
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* Even if we do not support configuring the modem control lines, this
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* function must be proided to the serial core
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*/
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}
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static void mvebu_uart_stop_tx(struct uart_port *port)
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{
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unsigned int ctl = readl(port->membase + UART_INTR(port));
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ctl &= ~CTRL_TX_RDY_INT(port);
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writel(ctl, port->membase + UART_INTR(port));
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}
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static void mvebu_uart_start_tx(struct uart_port *port)
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{
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unsigned int ctl;
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struct circ_buf *xmit = &port->state->xmit;
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if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
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writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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ctl = readl(port->membase + UART_INTR(port));
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ctl |= CTRL_TX_RDY_INT(port);
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writel(ctl, port->membase + UART_INTR(port));
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}
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static void mvebu_uart_stop_rx(struct uart_port *port)
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{
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unsigned int ctl;
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ctl = readl(port->membase + UART_CTRL(port));
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ctl &= ~CTRL_BRK_INT;
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writel(ctl, port->membase + UART_CTRL(port));
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ctl = readl(port->membase + UART_INTR(port));
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ctl &= ~CTRL_RX_RDY_INT(port);
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writel(ctl, port->membase + UART_INTR(port));
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}
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static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
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{
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unsigned int ctl;
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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ctl = readl(port->membase + UART_CTRL(port));
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if (brk == -1)
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ctl |= CTRL_SND_BRK_SEQ;
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else
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ctl &= ~CTRL_SND_BRK_SEQ;
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writel(ctl, port->membase + UART_CTRL(port));
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spin_unlock_irqrestore(&port->lock, flags);
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}
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static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
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{
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struct tty_port *tport = &port->state->port;
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unsigned char ch = 0;
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char flag = 0;
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do {
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if (status & STAT_RX_RDY(port)) {
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ch = readl(port->membase + UART_RBR(port));
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ch &= 0xff;
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flag = TTY_NORMAL;
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port->icount.rx++;
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if (status & STAT_PAR_ERR)
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port->icount.parity++;
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}
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if (status & STAT_BRK_DET) {
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port->icount.brk++;
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status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
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if (uart_handle_break(port))
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goto ignore_char;
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}
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if (status & STAT_OVR_ERR)
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port->icount.overrun++;
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if (status & STAT_FRM_ERR)
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port->icount.frame++;
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if (uart_handle_sysrq_char(port, ch))
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goto ignore_char;
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if (status & port->ignore_status_mask & STAT_PAR_ERR)
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status &= ~STAT_RX_RDY(port);
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status &= port->read_status_mask;
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if (status & STAT_PAR_ERR)
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flag = TTY_PARITY;
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status &= ~port->ignore_status_mask;
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if (status & STAT_RX_RDY(port))
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tty_insert_flip_char(tport, ch, flag);
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if (status & STAT_BRK_DET)
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tty_insert_flip_char(tport, 0, TTY_BREAK);
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if (status & STAT_FRM_ERR)
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tty_insert_flip_char(tport, 0, TTY_FRAME);
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if (status & STAT_OVR_ERR)
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tty_insert_flip_char(tport, 0, TTY_OVERRUN);
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ignore_char:
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status = readl(port->membase + UART_STAT);
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} while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
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tty_flip_buffer_push(tport);
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}
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static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
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{
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struct circ_buf *xmit = &port->state->xmit;
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unsigned int count;
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unsigned int st;
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if (port->x_char) {
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writel(port->x_char, port->membase + UART_TSH(port));
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port->icount.tx++;
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port->x_char = 0;
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return;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
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mvebu_uart_stop_tx(port);
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return;
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}
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for (count = 0; count < port->fifosize; count++) {
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writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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if (uart_circ_empty(xmit))
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break;
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st = readl(port->membase + UART_STAT);
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if (st & STAT_TX_FIFO_FUL)
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break;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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if (uart_circ_empty(xmit))
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mvebu_uart_stop_tx(port);
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}
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static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
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{
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struct uart_port *port = (struct uart_port *)dev_id;
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unsigned int st = readl(port->membase + UART_STAT);
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if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
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STAT_BRK_DET))
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mvebu_uart_rx_chars(port, st);
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if (st & STAT_TX_RDY(port))
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mvebu_uart_tx_chars(port, st);
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return IRQ_HANDLED;
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}
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static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
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{
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struct uart_port *port = (struct uart_port *)dev_id;
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unsigned int st = readl(port->membase + UART_STAT);
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if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
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STAT_BRK_DET))
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mvebu_uart_rx_chars(port, st);
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return IRQ_HANDLED;
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}
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static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
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{
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struct uart_port *port = (struct uart_port *)dev_id;
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unsigned int st = readl(port->membase + UART_STAT);
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if (st & STAT_TX_RDY(port))
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mvebu_uart_tx_chars(port, st);
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return IRQ_HANDLED;
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}
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static int mvebu_uart_startup(struct uart_port *port)
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{
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struct mvebu_uart *mvuart = to_mvuart(port);
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unsigned int ctl;
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int ret;
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writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
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port->membase + UART_CTRL(port));
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udelay(1);
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/* Clear the error bits of state register before IRQ request */
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ret = readl(port->membase + UART_STAT);
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ret |= STAT_BRK_ERR;
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writel(ret, port->membase + UART_STAT);
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writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
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ctl = readl(port->membase + UART_INTR(port));
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ctl |= CTRL_RX_RDY_INT(port);
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writel(ctl, port->membase + UART_INTR(port));
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if (!mvuart->irq[UART_TX_IRQ]) {
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/* Old bindings with just one interrupt (UART0 only) */
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ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
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mvebu_uart_isr, port->irqflags,
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dev_name(port->dev), port);
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if (ret) {
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dev_err(port->dev, "unable to request IRQ %d\n",
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mvuart->irq[UART_IRQ_SUM]);
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return ret;
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}
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} else {
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/* New bindings with an IRQ for RX and TX (both UART) */
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ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
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mvebu_uart_rx_isr, port->irqflags,
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dev_name(port->dev), port);
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if (ret) {
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dev_err(port->dev, "unable to request IRQ %d\n",
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mvuart->irq[UART_RX_IRQ]);
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return ret;
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}
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ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
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mvebu_uart_tx_isr, port->irqflags,
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dev_name(port->dev),
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port);
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if (ret) {
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dev_err(port->dev, "unable to request IRQ %d\n",
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mvuart->irq[UART_TX_IRQ]);
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devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
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port);
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return ret;
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}
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}
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return 0;
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}
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static void mvebu_uart_shutdown(struct uart_port *port)
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{
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struct mvebu_uart *mvuart = to_mvuart(port);
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writel(0, port->membase + UART_INTR(port));
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if (!mvuart->irq[UART_TX_IRQ]) {
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devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
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} else {
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devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
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devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
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}
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}
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static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
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{
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unsigned int d_divisor, m_divisor;
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u32 brdv, osamp;
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if (!port->uartclk)
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return -EOPNOTSUPP;
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/*
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* The baudrate is derived from the UART clock thanks to two divisors:
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* > D ("baud generator"): can divide the clock from 2 to 2^10 - 1.
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* > M ("fractional divisor"): allows a better accuracy for
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* baudrates higher than 230400.
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*
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* As the derivation of M is rather complicated, the code sticks to its
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* default value (x16) when all the prescalers are zeroed, and only
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* makes use of D to configure the desired baudrate.
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*/
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m_divisor = OSAMP_DEFAULT_DIVISOR;
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d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
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brdv = readl(port->membase + UART_BRDV);
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brdv &= ~BRDV_BAUD_MASK;
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brdv |= d_divisor;
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writel(brdv, port->membase + UART_BRDV);
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osamp = readl(port->membase + UART_OSAMP);
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osamp &= ~OSAMP_DIVISORS_MASK;
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writel(osamp, port->membase + UART_OSAMP);
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return 0;
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}
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static void mvebu_uart_set_termios(struct uart_port *port,
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struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned long flags;
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unsigned int baud, min_baud, max_baud;
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spin_lock_irqsave(&port->lock, flags);
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|
|
port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
|
|
STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
|
|
|
|
if (termios->c_iflag & INPCK)
|
|
port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
|
|
|
|
port->ignore_status_mask = 0;
|
|
if (termios->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |=
|
|
STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
|
|
|
|
if ((termios->c_cflag & CREAD) == 0)
|
|
port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
|
|
|
|
/*
|
|
* Maximal divisor is 1023 * 16 when using default (x16) scheme.
|
|
* Maximum achievable frequency with simple baudrate divisor is 230400.
|
|
* Since the error per bit frame would be of more than 15%, achieving
|
|
* higher frequencies would require to implement the fractional divisor
|
|
* feature.
|
|
*/
|
|
min_baud = DIV_ROUND_UP(port->uartclk, 1023 * 16);
|
|
max_baud = 230400;
|
|
|
|
baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud);
|
|
if (mvebu_uart_baud_rate_set(port, baud)) {
|
|
/* No clock available, baudrate cannot be changed */
|
|
if (old)
|
|
baud = uart_get_baud_rate(port, old, NULL,
|
|
min_baud, max_baud);
|
|
} else {
|
|
tty_termios_encode_baud_rate(termios, baud, baud);
|
|
uart_update_timeout(port, termios->c_cflag, baud);
|
|
}
|
|
|
|
/* Only the following flag changes are supported */
|
|
if (old) {
|
|
termios->c_iflag &= INPCK | IGNPAR;
|
|
termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
|
|
termios->c_cflag &= CREAD | CBAUD;
|
|
termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
|
|
termios->c_cflag |= CS8;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
}
|
|
|
|
static const char *mvebu_uart_type(struct uart_port *port)
|
|
{
|
|
return MVEBU_UART_TYPE;
|
|
}
|
|
|
|
static void mvebu_uart_release_port(struct uart_port *port)
|
|
{
|
|
/* Nothing to do here */
|
|
}
|
|
|
|
static int mvebu_uart_request_port(struct uart_port *port)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_CONSOLE_POLL
|
|
static int mvebu_uart_get_poll_char(struct uart_port *port)
|
|
{
|
|
unsigned int st = readl(port->membase + UART_STAT);
|
|
|
|
if (!(st & STAT_RX_RDY(port)))
|
|
return NO_POLL_CHAR;
|
|
|
|
return readl(port->membase + UART_RBR(port));
|
|
}
|
|
|
|
static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
|
|
{
|
|
unsigned int st;
|
|
|
|
for (;;) {
|
|
st = readl(port->membase + UART_STAT);
|
|
|
|
if (!(st & STAT_TX_FIFO_FUL))
|
|
break;
|
|
|
|
udelay(1);
|
|
}
|
|
|
|
writel(c, port->membase + UART_TSH(port));
|
|
}
|
|
#endif
|
|
|
|
static const struct uart_ops mvebu_uart_ops = {
|
|
.tx_empty = mvebu_uart_tx_empty,
|
|
.set_mctrl = mvebu_uart_set_mctrl,
|
|
.get_mctrl = mvebu_uart_get_mctrl,
|
|
.stop_tx = mvebu_uart_stop_tx,
|
|
.start_tx = mvebu_uart_start_tx,
|
|
.stop_rx = mvebu_uart_stop_rx,
|
|
.break_ctl = mvebu_uart_break_ctl,
|
|
.startup = mvebu_uart_startup,
|
|
.shutdown = mvebu_uart_shutdown,
|
|
.set_termios = mvebu_uart_set_termios,
|
|
.type = mvebu_uart_type,
|
|
.release_port = mvebu_uart_release_port,
|
|
.request_port = mvebu_uart_request_port,
|
|
#ifdef CONFIG_CONSOLE_POLL
|
|
.poll_get_char = mvebu_uart_get_poll_char,
|
|
.poll_put_char = mvebu_uart_put_poll_char,
|
|
#endif
|
|
};
|
|
|
|
/* Console Driver Operations */
|
|
|
|
#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
|
|
/* Early Console */
|
|
static void mvebu_uart_putc(struct uart_port *port, int c)
|
|
{
|
|
unsigned int st;
|
|
|
|
for (;;) {
|
|
st = readl(port->membase + UART_STAT);
|
|
if (!(st & STAT_TX_FIFO_FUL))
|
|
break;
|
|
}
|
|
|
|
/* At early stage, DT is not parsed yet, only use UART0 */
|
|
writel(c, port->membase + UART_STD_TSH);
|
|
|
|
for (;;) {
|
|
st = readl(port->membase + UART_STAT);
|
|
if (st & STAT_TX_FIFO_EMP)
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void mvebu_uart_putc_early_write(struct console *con,
|
|
const char *s,
|
|
unsigned int n)
|
|
{
|
|
struct earlycon_device *dev = con->data;
|
|
|
|
uart_console_write(&dev->port, s, n, mvebu_uart_putc);
|
|
}
|
|
|
|
static int __init
|
|
mvebu_uart_early_console_setup(struct earlycon_device *device,
|
|
const char *opt)
|
|
{
|
|
if (!device->port.membase)
|
|
return -ENODEV;
|
|
|
|
device->con->write = mvebu_uart_putc_early_write;
|
|
|
|
return 0;
|
|
}
|
|
|
|
EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
|
|
OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
|
|
mvebu_uart_early_console_setup);
|
|
|
|
static void wait_for_xmitr(struct uart_port *port)
|
|
{
|
|
u32 val;
|
|
|
|
readl_poll_timeout_atomic(port->membase + UART_STAT, val,
|
|
(val & STAT_TX_RDY(port)), 1, 10000);
|
|
}
|
|
|
|
static void wait_for_xmite(struct uart_port *port)
|
|
{
|
|
u32 val;
|
|
|
|
readl_poll_timeout_atomic(port->membase + UART_STAT, val,
|
|
(val & STAT_TX_EMP), 1, 10000);
|
|
}
|
|
|
|
static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
wait_for_xmitr(port);
|
|
writel(ch, port->membase + UART_TSH(port));
|
|
}
|
|
|
|
static void mvebu_uart_console_write(struct console *co, const char *s,
|
|
unsigned int count)
|
|
{
|
|
struct uart_port *port = &mvebu_uart_ports[co->index];
|
|
unsigned long flags;
|
|
unsigned int ier, intr, ctl;
|
|
int locked = 1;
|
|
|
|
if (oops_in_progress)
|
|
locked = spin_trylock_irqsave(&port->lock, flags);
|
|
else
|
|
spin_lock_irqsave(&port->lock, flags);
|
|
|
|
ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
|
|
intr = readl(port->membase + UART_INTR(port)) &
|
|
(CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
|
|
writel(0, port->membase + UART_CTRL(port));
|
|
writel(0, port->membase + UART_INTR(port));
|
|
|
|
uart_console_write(port, s, count, mvebu_uart_console_putchar);
|
|
|
|
wait_for_xmite(port);
|
|
|
|
if (ier)
|
|
writel(ier, port->membase + UART_CTRL(port));
|
|
|
|
if (intr) {
|
|
ctl = intr | readl(port->membase + UART_INTR(port));
|
|
writel(ctl, port->membase + UART_INTR(port));
|
|
}
|
|
|
|
if (locked)
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
}
|
|
|
|
static int mvebu_uart_console_setup(struct console *co, char *options)
|
|
{
|
|
struct uart_port *port;
|
|
int baud = 9600;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
|
|
return -EINVAL;
|
|
|
|
port = &mvebu_uart_ports[co->index];
|
|
|
|
if (!port->mapbase || !port->membase) {
|
|
pr_debug("console on ttyMV%i not present\n", co->index);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
return uart_set_options(port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct uart_driver mvebu_uart_driver;
|
|
|
|
static struct console mvebu_uart_console = {
|
|
.name = "ttyMV",
|
|
.write = mvebu_uart_console_write,
|
|
.device = uart_console_device,
|
|
.setup = mvebu_uart_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &mvebu_uart_driver,
|
|
};
|
|
|
|
static int __init mvebu_uart_console_init(void)
|
|
{
|
|
register_console(&mvebu_uart_console);
|
|
return 0;
|
|
}
|
|
|
|
console_initcall(mvebu_uart_console_init);
|
|
|
|
|
|
#endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
|
|
|
|
static struct uart_driver mvebu_uart_driver = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = DRIVER_NAME,
|
|
.dev_name = "ttyMV",
|
|
.nr = MVEBU_NR_UARTS,
|
|
#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
|
|
.cons = &mvebu_uart_console,
|
|
#endif
|
|
};
|
|
|
|
#if defined(CONFIG_PM)
|
|
static int mvebu_uart_suspend(struct device *dev)
|
|
{
|
|
struct mvebu_uart *mvuart = dev_get_drvdata(dev);
|
|
struct uart_port *port = mvuart->port;
|
|
|
|
uart_suspend_port(&mvebu_uart_driver, port);
|
|
|
|
mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
|
|
mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
|
|
mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
|
|
mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
|
|
mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
|
|
mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
|
|
mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
|
|
|
|
device_set_wakeup_enable(dev, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mvebu_uart_resume(struct device *dev)
|
|
{
|
|
struct mvebu_uart *mvuart = dev_get_drvdata(dev);
|
|
struct uart_port *port = mvuart->port;
|
|
|
|
writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
|
|
writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
|
|
writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
|
|
writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
|
|
writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
|
|
writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
|
|
writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
|
|
|
|
uart_resume_port(&mvebu_uart_driver, port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops mvebu_uart_pm_ops = {
|
|
.suspend = mvebu_uart_suspend,
|
|
.resume = mvebu_uart_resume,
|
|
};
|
|
#endif /* CONFIG_PM */
|
|
|
|
static const struct of_device_id mvebu_uart_of_match[];
|
|
|
|
/* Counter to keep track of each UART port id when not using CONFIG_OF */
|
|
static int uart_num_counter;
|
|
|
|
static int mvebu_uart_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
|
|
&pdev->dev);
|
|
struct uart_port *port;
|
|
struct mvebu_uart *mvuart;
|
|
int id, irq;
|
|
|
|
if (!reg) {
|
|
dev_err(&pdev->dev, "no registers defined\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Assume that all UART ports have a DT alias or none has */
|
|
id = of_alias_get_id(pdev->dev.of_node, "serial");
|
|
if (!pdev->dev.of_node || id < 0)
|
|
pdev->id = uart_num_counter++;
|
|
else
|
|
pdev->id = id;
|
|
|
|
if (pdev->id >= MVEBU_NR_UARTS) {
|
|
dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
|
|
MVEBU_NR_UARTS);
|
|
return -EINVAL;
|
|
}
|
|
|
|
port = &mvebu_uart_ports[pdev->id];
|
|
|
|
spin_lock_init(&port->lock);
|
|
|
|
port->dev = &pdev->dev;
|
|
port->type = PORT_MVEBU;
|
|
port->ops = &mvebu_uart_ops;
|
|
port->regshift = 0;
|
|
|
|
port->fifosize = 32;
|
|
port->iotype = UPIO_MEM32;
|
|
port->flags = UPF_FIXED_PORT;
|
|
port->line = pdev->id;
|
|
|
|
/*
|
|
* IRQ number is not stored in this structure because we may have two of
|
|
* them per port (RX and TX). Instead, use the driver UART structure
|
|
* array so called ->irq[].
|
|
*/
|
|
port->irq = 0;
|
|
port->irqflags = 0;
|
|
port->mapbase = reg->start;
|
|
|
|
port->membase = devm_ioremap_resource(&pdev->dev, reg);
|
|
if (IS_ERR(port->membase))
|
|
return PTR_ERR(port->membase);
|
|
|
|
mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
|
|
GFP_KERNEL);
|
|
if (!mvuart)
|
|
return -ENOMEM;
|
|
|
|
/* Get controller data depending on the compatible string */
|
|
mvuart->data = (struct mvebu_uart_driver_data *)match->data;
|
|
mvuart->port = port;
|
|
|
|
port->private_data = mvuart;
|
|
platform_set_drvdata(pdev, mvuart);
|
|
|
|
/* Get fixed clock frequency */
|
|
mvuart->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(mvuart->clk)) {
|
|
if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
|
|
return PTR_ERR(mvuart->clk);
|
|
|
|
if (IS_EXTENDED(port)) {
|
|
dev_err(&pdev->dev, "unable to get UART clock\n");
|
|
return PTR_ERR(mvuart->clk);
|
|
}
|
|
} else {
|
|
if (!clk_prepare_enable(mvuart->clk))
|
|
port->uartclk = clk_get_rate(mvuart->clk);
|
|
}
|
|
|
|
/* Manage interrupts */
|
|
if (platform_irq_count(pdev) == 1) {
|
|
/* Old bindings: no name on the single unamed UART0 IRQ */
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
mvuart->irq[UART_IRQ_SUM] = irq;
|
|
} else {
|
|
/*
|
|
* New bindings: named interrupts (RX, TX) for both UARTS,
|
|
* only make use of uart-rx and uart-tx interrupts, do not use
|
|
* uart-sum of UART0 port.
|
|
*/
|
|
irq = platform_get_irq_byname(pdev, "uart-rx");
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
mvuart->irq[UART_RX_IRQ] = irq;
|
|
|
|
irq = platform_get_irq_byname(pdev, "uart-tx");
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
mvuart->irq[UART_TX_IRQ] = irq;
|
|
}
|
|
|
|
/* UART Soft Reset*/
|
|
writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
|
|
udelay(1);
|
|
writel(0, port->membase + UART_CTRL(port));
|
|
|
|
return uart_add_one_port(&mvebu_uart_driver, port);
|
|
}
|
|
|
|
static struct mvebu_uart_driver_data uart_std_driver_data = {
|
|
.is_ext = false,
|
|
.regs.rbr = UART_STD_RBR,
|
|
.regs.tsh = UART_STD_TSH,
|
|
.regs.ctrl = UART_STD_CTRL1,
|
|
.regs.intr = UART_STD_CTRL2,
|
|
.flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
|
|
.flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
|
|
.flags.stat_tx_rdy = STAT_STD_TX_RDY,
|
|
.flags.stat_rx_rdy = STAT_STD_RX_RDY,
|
|
};
|
|
|
|
static struct mvebu_uart_driver_data uart_ext_driver_data = {
|
|
.is_ext = true,
|
|
.regs.rbr = UART_EXT_RBR,
|
|
.regs.tsh = UART_EXT_TSH,
|
|
.regs.ctrl = UART_EXT_CTRL1,
|
|
.regs.intr = UART_EXT_CTRL2,
|
|
.flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
|
|
.flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
|
|
.flags.stat_tx_rdy = STAT_EXT_TX_RDY,
|
|
.flags.stat_rx_rdy = STAT_EXT_RX_RDY,
|
|
};
|
|
|
|
/* Match table for of_platform binding */
|
|
static const struct of_device_id mvebu_uart_of_match[] = {
|
|
{
|
|
.compatible = "marvell,armada-3700-uart",
|
|
.data = (void *)&uart_std_driver_data,
|
|
},
|
|
{
|
|
.compatible = "marvell,armada-3700-uart-ext",
|
|
.data = (void *)&uart_ext_driver_data,
|
|
},
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver mvebu_uart_platform_driver = {
|
|
.probe = mvebu_uart_probe,
|
|
.driver = {
|
|
.name = "mvebu-uart",
|
|
.of_match_table = of_match_ptr(mvebu_uart_of_match),
|
|
.suppress_bind_attrs = true,
|
|
#if defined(CONFIG_PM)
|
|
.pm = &mvebu_uart_pm_ops,
|
|
#endif /* CONFIG_PM */
|
|
},
|
|
};
|
|
|
|
static int __init mvebu_uart_init(void)
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{
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int ret;
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ret = uart_register_driver(&mvebu_uart_driver);
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if (ret)
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return ret;
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ret = platform_driver_register(&mvebu_uart_platform_driver);
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if (ret)
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uart_unregister_driver(&mvebu_uart_driver);
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return ret;
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}
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arch_initcall(mvebu_uart_init);
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