949 строки
22 KiB
C
949 строки
22 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* uartlite.c: Serial driver for Xilinx uartlite serial controller
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*
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* Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
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* Copyright (C) 2007 Secret Lab Technologies Ltd.
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*/
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/bitfield.h>
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#include <linux/console.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#define ULITE_NAME "ttyUL"
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#define ULITE_MAJOR 204
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#define ULITE_MINOR 187
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#define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS
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/* ---------------------------------------------------------------------
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* Register definitions
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*
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* For register details see datasheet:
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* https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
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*/
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#define ULITE_RX 0x00
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#define ULITE_TX 0x04
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#define ULITE_STATUS 0x08
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#define ULITE_CONTROL 0x0c
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#define ULITE_REGION 16
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#define ULITE_STATUS_RXVALID 0x01
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#define ULITE_STATUS_RXFULL 0x02
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#define ULITE_STATUS_TXEMPTY 0x04
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#define ULITE_STATUS_TXFULL 0x08
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#define ULITE_STATUS_IE 0x10
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#define ULITE_STATUS_OVERRUN 0x20
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#define ULITE_STATUS_FRAME 0x40
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#define ULITE_STATUS_PARITY 0x80
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#define ULITE_CONTROL_RST_TX 0x01
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#define ULITE_CONTROL_RST_RX 0x02
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#define ULITE_CONTROL_IE 0x10
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#define UART_AUTOSUSPEND_TIMEOUT 3000 /* ms */
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/* Static pointer to console port */
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#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
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static struct uart_port *console_port;
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#endif
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/**
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* struct uartlite_data: Driver private data
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* reg_ops: Functions to read/write registers
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* clk: Our parent clock, if present
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* baud: The baud rate configured when this device was synthesized
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* cflags: The cflags for parity and data bits
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*/
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struct uartlite_data {
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const struct uartlite_reg_ops *reg_ops;
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struct clk *clk;
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unsigned int baud;
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tcflag_t cflags;
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};
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struct uartlite_reg_ops {
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u32 (*in)(void __iomem *addr);
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void (*out)(u32 val, void __iomem *addr);
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};
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static u32 uartlite_inbe32(void __iomem *addr)
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{
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return ioread32be(addr);
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}
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static void uartlite_outbe32(u32 val, void __iomem *addr)
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{
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iowrite32be(val, addr);
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}
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static const struct uartlite_reg_ops uartlite_be = {
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.in = uartlite_inbe32,
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.out = uartlite_outbe32,
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};
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static u32 uartlite_inle32(void __iomem *addr)
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{
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return ioread32(addr);
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}
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static void uartlite_outle32(u32 val, void __iomem *addr)
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{
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iowrite32(val, addr);
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}
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static const struct uartlite_reg_ops uartlite_le = {
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.in = uartlite_inle32,
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.out = uartlite_outle32,
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};
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static inline u32 uart_in32(u32 offset, struct uart_port *port)
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{
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struct uartlite_data *pdata = port->private_data;
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return pdata->reg_ops->in(port->membase + offset);
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}
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static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
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{
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struct uartlite_data *pdata = port->private_data;
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pdata->reg_ops->out(val, port->membase + offset);
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}
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static struct uart_port ulite_ports[ULITE_NR_UARTS];
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static struct uart_driver ulite_uart_driver;
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/* ---------------------------------------------------------------------
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* Core UART driver operations
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*/
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static int ulite_receive(struct uart_port *port, int stat)
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{
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struct tty_port *tport = &port->state->port;
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unsigned char ch = 0;
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char flag = TTY_NORMAL;
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if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
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| ULITE_STATUS_FRAME)) == 0)
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return 0;
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/* stats */
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if (stat & ULITE_STATUS_RXVALID) {
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port->icount.rx++;
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ch = uart_in32(ULITE_RX, port);
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if (stat & ULITE_STATUS_PARITY)
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port->icount.parity++;
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}
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if (stat & ULITE_STATUS_OVERRUN)
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port->icount.overrun++;
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if (stat & ULITE_STATUS_FRAME)
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port->icount.frame++;
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/* drop byte with parity error if IGNPAR specificed */
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if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
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stat &= ~ULITE_STATUS_RXVALID;
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stat &= port->read_status_mask;
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if (stat & ULITE_STATUS_PARITY)
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flag = TTY_PARITY;
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stat &= ~port->ignore_status_mask;
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if (stat & ULITE_STATUS_RXVALID)
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tty_insert_flip_char(tport, ch, flag);
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if (stat & ULITE_STATUS_FRAME)
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tty_insert_flip_char(tport, 0, TTY_FRAME);
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if (stat & ULITE_STATUS_OVERRUN)
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tty_insert_flip_char(tport, 0, TTY_OVERRUN);
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return 1;
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}
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static int ulite_transmit(struct uart_port *port, int stat)
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{
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struct circ_buf *xmit = &port->state->xmit;
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if (stat & ULITE_STATUS_TXFULL)
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return 0;
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if (port->x_char) {
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uart_out32(port->x_char, ULITE_TX, port);
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port->x_char = 0;
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port->icount.tx++;
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return 1;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(port))
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return 0;
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uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
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port->icount.tx++;
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/* wake up */
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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return 1;
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}
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static irqreturn_t ulite_isr(int irq, void *dev_id)
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{
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struct uart_port *port = dev_id;
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int stat, busy, n = 0;
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unsigned long flags;
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do {
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spin_lock_irqsave(&port->lock, flags);
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stat = uart_in32(ULITE_STATUS, port);
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busy = ulite_receive(port, stat);
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busy |= ulite_transmit(port, stat);
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spin_unlock_irqrestore(&port->lock, flags);
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n++;
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} while (busy);
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/* work done? */
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if (n > 1) {
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tty_flip_buffer_push(&port->state->port);
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return IRQ_HANDLED;
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} else {
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return IRQ_NONE;
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}
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}
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static unsigned int ulite_tx_empty(struct uart_port *port)
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{
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unsigned long flags;
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unsigned int ret;
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spin_lock_irqsave(&port->lock, flags);
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ret = uart_in32(ULITE_STATUS, port);
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spin_unlock_irqrestore(&port->lock, flags);
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return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
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}
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static unsigned int ulite_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
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}
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static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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/* N/A */
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}
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static void ulite_stop_tx(struct uart_port *port)
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{
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/* N/A */
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}
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static void ulite_start_tx(struct uart_port *port)
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{
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ulite_transmit(port, uart_in32(ULITE_STATUS, port));
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}
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static void ulite_stop_rx(struct uart_port *port)
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{
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/* don't forward any more data (like !CREAD) */
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port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
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| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
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}
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static void ulite_break_ctl(struct uart_port *port, int ctl)
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{
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/* N/A */
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}
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static int ulite_startup(struct uart_port *port)
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{
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struct uartlite_data *pdata = port->private_data;
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int ret;
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ret = clk_enable(pdata->clk);
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if (ret) {
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dev_err(port->dev, "Failed to enable clock\n");
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return ret;
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}
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ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING,
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"uartlite", port);
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if (ret)
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return ret;
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uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
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ULITE_CONTROL, port);
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uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
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return 0;
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}
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static void ulite_shutdown(struct uart_port *port)
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{
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struct uartlite_data *pdata = port->private_data;
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uart_out32(0, ULITE_CONTROL, port);
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uart_in32(ULITE_CONTROL, port); /* dummy */
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free_irq(port->irq, port);
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clk_disable(pdata->clk);
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}
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static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned long flags;
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struct uartlite_data *pdata = port->private_data;
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/* Set termios to what the hardware supports */
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termios->c_cflag &= ~(BRKINT | CSTOPB | PARENB | PARODD | CSIZE);
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termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE);
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tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud);
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spin_lock_irqsave(&port->lock, flags);
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port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
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| ULITE_STATUS_TXFULL;
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if (termios->c_iflag & INPCK)
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port->read_status_mask |=
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ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
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port->ignore_status_mask = 0;
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if (termios->c_iflag & IGNPAR)
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port->ignore_status_mask |= ULITE_STATUS_PARITY
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| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
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/* ignore all characters if CREAD is not set */
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if ((termios->c_cflag & CREAD) == 0)
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port->ignore_status_mask |=
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ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
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| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
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/* update timeout */
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uart_update_timeout(port, termios->c_cflag, pdata->baud);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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static const char *ulite_type(struct uart_port *port)
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{
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return port->type == PORT_UARTLITE ? "uartlite" : NULL;
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}
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static void ulite_release_port(struct uart_port *port)
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{
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release_mem_region(port->mapbase, ULITE_REGION);
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iounmap(port->membase);
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port->membase = NULL;
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}
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static int ulite_request_port(struct uart_port *port)
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{
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struct uartlite_data *pdata = port->private_data;
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int ret;
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pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
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port, (unsigned long long) port->mapbase);
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if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
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dev_err(port->dev, "Memory region busy\n");
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return -EBUSY;
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}
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port->membase = ioremap(port->mapbase, ULITE_REGION);
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if (!port->membase) {
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dev_err(port->dev, "Unable to map registers\n");
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release_mem_region(port->mapbase, ULITE_REGION);
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return -EBUSY;
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}
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pdata->reg_ops = &uartlite_be;
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ret = uart_in32(ULITE_CONTROL, port);
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uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
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ret = uart_in32(ULITE_STATUS, port);
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/* Endianess detection */
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if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
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pdata->reg_ops = &uartlite_le;
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return 0;
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}
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static void ulite_config_port(struct uart_port *port, int flags)
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{
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if (!ulite_request_port(port))
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port->type = PORT_UARTLITE;
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}
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static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
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{
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/* we don't want the core code to modify any port params */
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return -EINVAL;
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}
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static void ulite_pm(struct uart_port *port, unsigned int state,
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unsigned int oldstate)
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{
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int ret;
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if (!state) {
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ret = pm_runtime_get_sync(port->dev);
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if (ret < 0)
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dev_err(port->dev, "Failed to enable clocks\n");
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} else {
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pm_runtime_mark_last_busy(port->dev);
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pm_runtime_put_autosuspend(port->dev);
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}
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}
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#ifdef CONFIG_CONSOLE_POLL
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static int ulite_get_poll_char(struct uart_port *port)
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{
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if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
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return NO_POLL_CHAR;
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return uart_in32(ULITE_RX, port);
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}
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static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
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{
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while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
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cpu_relax();
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/* write char to device */
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uart_out32(ch, ULITE_TX, port);
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}
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#endif
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static const struct uart_ops ulite_ops = {
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.tx_empty = ulite_tx_empty,
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.set_mctrl = ulite_set_mctrl,
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.get_mctrl = ulite_get_mctrl,
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.stop_tx = ulite_stop_tx,
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.start_tx = ulite_start_tx,
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.stop_rx = ulite_stop_rx,
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.break_ctl = ulite_break_ctl,
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.startup = ulite_startup,
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.shutdown = ulite_shutdown,
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.set_termios = ulite_set_termios,
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.type = ulite_type,
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.release_port = ulite_release_port,
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.request_port = ulite_request_port,
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.config_port = ulite_config_port,
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.verify_port = ulite_verify_port,
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.pm = ulite_pm,
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#ifdef CONFIG_CONSOLE_POLL
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.poll_get_char = ulite_get_poll_char,
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.poll_put_char = ulite_put_poll_char,
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#endif
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};
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/* ---------------------------------------------------------------------
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* Console driver operations
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*/
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#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
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static void ulite_console_wait_tx(struct uart_port *port)
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{
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u8 val;
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/*
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* Spin waiting for TX fifo to have space available.
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* When using the Microblaze Debug Module this can take up to 1s
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*/
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if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL),
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0, 1000000, false, ULITE_STATUS, port))
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dev_warn(port->dev,
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"timeout waiting for TX buffer empty\n");
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}
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static void ulite_console_putchar(struct uart_port *port, int ch)
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{
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ulite_console_wait_tx(port);
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uart_out32(ch, ULITE_TX, port);
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}
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static void ulite_console_write(struct console *co, const char *s,
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unsigned int count)
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{
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struct uart_port *port = console_port;
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unsigned long flags;
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unsigned int ier;
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int locked = 1;
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if (oops_in_progress) {
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locked = spin_trylock_irqsave(&port->lock, flags);
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} else
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spin_lock_irqsave(&port->lock, flags);
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/* save and disable interrupt */
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ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
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uart_out32(0, ULITE_CONTROL, port);
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uart_console_write(port, s, count, ulite_console_putchar);
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ulite_console_wait_tx(port);
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/* restore interrupt state */
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if (ier)
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uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
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if (locked)
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spin_unlock_irqrestore(&port->lock, flags);
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}
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static int ulite_console_setup(struct console *co, char *options)
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{
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struct uart_port *port = NULL;
|
|
int baud = 9600;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
if (co->index >= 0 && co->index < ULITE_NR_UARTS)
|
|
port = ulite_ports + co->index;
|
|
|
|
/* Has the device been initialized yet? */
|
|
if (!port || !port->mapbase) {
|
|
pr_debug("console on ttyUL%i not present\n", co->index);
|
|
return -ENODEV;
|
|
}
|
|
|
|
console_port = port;
|
|
|
|
/* not initialized yet? */
|
|
if (!port->membase) {
|
|
if (ulite_request_port(port))
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
return uart_set_options(port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct console ulite_console = {
|
|
.name = ULITE_NAME,
|
|
.write = ulite_console_write,
|
|
.device = uart_console_device,
|
|
.setup = ulite_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
|
|
.data = &ulite_uart_driver,
|
|
};
|
|
|
|
static void early_uartlite_putc(struct uart_port *port, int c)
|
|
{
|
|
/*
|
|
* Limit how many times we'll spin waiting for TX FIFO status.
|
|
* This will prevent lockups if the base address is incorrectly
|
|
* set, or any other issue on the UARTLITE.
|
|
* This limit is pretty arbitrary, unless we are at about 10 baud
|
|
* we'll never timeout on a working UART.
|
|
*/
|
|
unsigned retries = 1000000;
|
|
|
|
while (--retries &&
|
|
(readl(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL))
|
|
;
|
|
|
|
/* Only attempt the iowrite if we didn't timeout */
|
|
if (retries)
|
|
writel(c & 0xff, port->membase + ULITE_TX);
|
|
}
|
|
|
|
static void early_uartlite_write(struct console *console,
|
|
const char *s, unsigned n)
|
|
{
|
|
struct earlycon_device *device = console->data;
|
|
uart_console_write(&device->port, s, n, early_uartlite_putc);
|
|
}
|
|
|
|
static int __init early_uartlite_setup(struct earlycon_device *device,
|
|
const char *options)
|
|
{
|
|
if (!device->port.membase)
|
|
return -ENODEV;
|
|
|
|
device->con->write = early_uartlite_write;
|
|
return 0;
|
|
}
|
|
EARLYCON_DECLARE(uartlite, early_uartlite_setup);
|
|
OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup);
|
|
OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup);
|
|
|
|
#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
|
|
|
|
static struct uart_driver ulite_uart_driver = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "uartlite",
|
|
.dev_name = ULITE_NAME,
|
|
.major = ULITE_MAJOR,
|
|
.minor = ULITE_MINOR,
|
|
.nr = ULITE_NR_UARTS,
|
|
#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
|
|
.cons = &ulite_console,
|
|
#endif
|
|
};
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* Port assignment functions (mapping devices to uart_port structures)
|
|
*/
|
|
|
|
/** ulite_assign: register a uartlite device with the driver
|
|
*
|
|
* @dev: pointer to device structure
|
|
* @id: requested id number. Pass -1 for automatic port assignment
|
|
* @base: base address of uartlite registers
|
|
* @irq: irq number for uartlite
|
|
* @pdata: private data for uartlite
|
|
*
|
|
* Returns: 0 on success, <0 otherwise
|
|
*/
|
|
static int ulite_assign(struct device *dev, int id, u32 base, int irq,
|
|
struct uartlite_data *pdata)
|
|
{
|
|
struct uart_port *port;
|
|
int rc;
|
|
|
|
/* if id = -1; then scan for a free id and use that */
|
|
if (id < 0) {
|
|
for (id = 0; id < ULITE_NR_UARTS; id++)
|
|
if (ulite_ports[id].mapbase == 0)
|
|
break;
|
|
}
|
|
if (id < 0 || id >= ULITE_NR_UARTS) {
|
|
dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
|
|
dev_err(dev, "cannot assign to %s%i; it is already in use\n",
|
|
ULITE_NAME, id);
|
|
return -EBUSY;
|
|
}
|
|
|
|
port = &ulite_ports[id];
|
|
|
|
spin_lock_init(&port->lock);
|
|
port->fifosize = 16;
|
|
port->regshift = 2;
|
|
port->iotype = UPIO_MEM;
|
|
port->iobase = 1; /* mark port in use */
|
|
port->mapbase = base;
|
|
port->membase = NULL;
|
|
port->ops = &ulite_ops;
|
|
port->irq = irq;
|
|
port->flags = UPF_BOOT_AUTOCONF;
|
|
port->dev = dev;
|
|
port->type = PORT_UNKNOWN;
|
|
port->line = id;
|
|
port->private_data = pdata;
|
|
|
|
dev_set_drvdata(dev, port);
|
|
|
|
/* Register the port */
|
|
rc = uart_add_one_port(&ulite_uart_driver, port);
|
|
if (rc) {
|
|
dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
|
|
port->mapbase = 0;
|
|
dev_set_drvdata(dev, NULL);
|
|
return rc;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/** ulite_release: register a uartlite device with the driver
|
|
*
|
|
* @dev: pointer to device structure
|
|
*/
|
|
static int ulite_release(struct device *dev)
|
|
{
|
|
struct uart_port *port = dev_get_drvdata(dev);
|
|
int rc = 0;
|
|
|
|
if (port) {
|
|
rc = uart_remove_one_port(&ulite_uart_driver, port);
|
|
dev_set_drvdata(dev, NULL);
|
|
port->mapbase = 0;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* ulite_suspend - Stop the device.
|
|
*
|
|
* @dev: handle to the device structure.
|
|
* Return: 0 always.
|
|
*/
|
|
static int __maybe_unused ulite_suspend(struct device *dev)
|
|
{
|
|
struct uart_port *port = dev_get_drvdata(dev);
|
|
|
|
if (port)
|
|
uart_suspend_port(&ulite_uart_driver, port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ulite_resume - Resume the device.
|
|
*
|
|
* @dev: handle to the device structure.
|
|
* Return: 0 on success, errno otherwise.
|
|
*/
|
|
static int __maybe_unused ulite_resume(struct device *dev)
|
|
{
|
|
struct uart_port *port = dev_get_drvdata(dev);
|
|
|
|
if (port)
|
|
uart_resume_port(&ulite_uart_driver, port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused ulite_runtime_suspend(struct device *dev)
|
|
{
|
|
struct uart_port *port = dev_get_drvdata(dev);
|
|
struct uartlite_data *pdata = port->private_data;
|
|
|
|
clk_disable(pdata->clk);
|
|
return 0;
|
|
};
|
|
|
|
static int __maybe_unused ulite_runtime_resume(struct device *dev)
|
|
{
|
|
struct uart_port *port = dev_get_drvdata(dev);
|
|
struct uartlite_data *pdata = port->private_data;
|
|
int ret;
|
|
|
|
ret = clk_enable(pdata->clk);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot enable clock.\n");
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* Platform bus binding
|
|
*/
|
|
|
|
static const struct dev_pm_ops ulite_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume)
|
|
SET_RUNTIME_PM_OPS(ulite_runtime_suspend,
|
|
ulite_runtime_resume, NULL)
|
|
};
|
|
|
|
#if defined(CONFIG_OF)
|
|
/* Match table for of_platform binding */
|
|
static const struct of_device_id ulite_of_match[] = {
|
|
{ .compatible = "xlnx,opb-uartlite-1.00.b", },
|
|
{ .compatible = "xlnx,xps-uartlite-1.00.a", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ulite_of_match);
|
|
#endif /* CONFIG_OF */
|
|
|
|
static int ulite_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
struct uartlite_data *pdata;
|
|
int irq, ret;
|
|
int id = pdev->id;
|
|
|
|
pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data),
|
|
GFP_KERNEL);
|
|
if (!pdata)
|
|
return -ENOMEM;
|
|
|
|
if (IS_ENABLED(CONFIG_OF)) {
|
|
const char *prop;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
u32 val = 0;
|
|
|
|
prop = "port-number";
|
|
ret = of_property_read_u32(np, prop, &id);
|
|
if (ret && ret != -EINVAL)
|
|
of_err:
|
|
return dev_err_probe(&pdev->dev, ret,
|
|
"could not read %s\n", prop);
|
|
|
|
prop = "current-speed";
|
|
ret = of_property_read_u32(np, prop, &pdata->baud);
|
|
if (ret)
|
|
goto of_err;
|
|
|
|
prop = "xlnx,use-parity";
|
|
ret = of_property_read_u32(np, prop, &val);
|
|
if (ret && ret != -EINVAL)
|
|
goto of_err;
|
|
|
|
if (val) {
|
|
prop = "xlnx,odd-parity";
|
|
ret = of_property_read_u32(np, prop, &val);
|
|
if (ret)
|
|
goto of_err;
|
|
|
|
if (val)
|
|
pdata->cflags |= PARODD;
|
|
pdata->cflags |= PARENB;
|
|
}
|
|
|
|
val = 8;
|
|
prop = "xlnx,data-bits";
|
|
ret = of_property_read_u32(np, prop, &val);
|
|
if (ret && ret != -EINVAL)
|
|
goto of_err;
|
|
|
|
switch (val) {
|
|
case 5:
|
|
pdata->cflags |= CS5;
|
|
break;
|
|
case 6:
|
|
pdata->cflags |= CS6;
|
|
break;
|
|
case 7:
|
|
pdata->cflags |= CS7;
|
|
break;
|
|
case 8:
|
|
pdata->cflags |= CS8;
|
|
break;
|
|
default:
|
|
return dev_err_probe(&pdev->dev, -EINVAL,
|
|
"bad data bits %d\n", val);
|
|
}
|
|
} else {
|
|
pdata->baud = 9600;
|
|
pdata->cflags = CS8;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -ENODEV;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
|
|
if (IS_ERR(pdata->clk)) {
|
|
if (PTR_ERR(pdata->clk) != -ENOENT)
|
|
return PTR_ERR(pdata->clk);
|
|
|
|
/*
|
|
* Clock framework support is optional, continue on
|
|
* anyways if we don't find a matching clock.
|
|
*/
|
|
pdata->clk = NULL;
|
|
}
|
|
|
|
ret = clk_prepare_enable(pdata->clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to prepare clock\n");
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
if (!ulite_uart_driver.state) {
|
|
dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n");
|
|
ret = uart_register_driver(&ulite_uart_driver);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to register driver\n");
|
|
clk_disable_unprepare(pdata->clk);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata);
|
|
|
|
pm_runtime_mark_last_busy(&pdev->dev);
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ulite_remove(struct platform_device *pdev)
|
|
{
|
|
struct uart_port *port = dev_get_drvdata(&pdev->dev);
|
|
struct uartlite_data *pdata = port->private_data;
|
|
int rc;
|
|
|
|
clk_disable_unprepare(pdata->clk);
|
|
rc = ulite_release(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
return rc;
|
|
}
|
|
|
|
/* work with hotplug and coldplug */
|
|
MODULE_ALIAS("platform:uartlite");
|
|
|
|
static struct platform_driver ulite_platform_driver = {
|
|
.probe = ulite_probe,
|
|
.remove = ulite_remove,
|
|
.driver = {
|
|
.name = "uartlite",
|
|
.of_match_table = of_match_ptr(ulite_of_match),
|
|
.pm = &ulite_pm_ops,
|
|
},
|
|
};
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* Module setup/teardown
|
|
*/
|
|
|
|
static int __init ulite_init(void)
|
|
{
|
|
|
|
pr_debug("uartlite: calling platform_driver_register()\n");
|
|
return platform_driver_register(&ulite_platform_driver);
|
|
}
|
|
|
|
static void __exit ulite_exit(void)
|
|
{
|
|
platform_driver_unregister(&ulite_platform_driver);
|
|
if (ulite_uart_driver.state)
|
|
uart_unregister_driver(&ulite_uart_driver);
|
|
}
|
|
|
|
module_init(ulite_init);
|
|
module_exit(ulite_exit);
|
|
|
|
MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
|
|
MODULE_DESCRIPTION("Xilinx uartlite serial driver");
|
|
MODULE_LICENSE("GPL");
|