940 строки
24 KiB
C
940 строки
24 KiB
C
/*
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* TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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*
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* Updated by Vinod & Sudhakar Feb 2005
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <linux/gpio.h>
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#include <linux/of_device.h>
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#include <linux/platform_data/i2c-davinci.h>
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/* ----- global defines ----------------------------------------------- */
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#define DAVINCI_I2C_TIMEOUT (1*HZ)
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#define DAVINCI_I2C_MAX_TRIES 2
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#define DAVINCI_I2C_OWN_ADDRESS 0x08
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#define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \
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DAVINCI_I2C_IMR_ARDY | \
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DAVINCI_I2C_IMR_NACK | \
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DAVINCI_I2C_IMR_AL)
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#define DAVINCI_I2C_OAR_REG 0x00
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#define DAVINCI_I2C_IMR_REG 0x04
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#define DAVINCI_I2C_STR_REG 0x08
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#define DAVINCI_I2C_CLKL_REG 0x0c
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#define DAVINCI_I2C_CLKH_REG 0x10
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#define DAVINCI_I2C_CNT_REG 0x14
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#define DAVINCI_I2C_DRR_REG 0x18
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#define DAVINCI_I2C_SAR_REG 0x1c
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#define DAVINCI_I2C_DXR_REG 0x20
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#define DAVINCI_I2C_MDR_REG 0x24
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#define DAVINCI_I2C_IVR_REG 0x28
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#define DAVINCI_I2C_EMDR_REG 0x2c
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#define DAVINCI_I2C_PSC_REG 0x30
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#define DAVINCI_I2C_FUNC_REG 0x48
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#define DAVINCI_I2C_DIR_REG 0x4c
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#define DAVINCI_I2C_DIN_REG 0x50
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#define DAVINCI_I2C_DOUT_REG 0x54
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#define DAVINCI_I2C_DSET_REG 0x58
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#define DAVINCI_I2C_DCLR_REG 0x5c
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#define DAVINCI_I2C_IVR_AAS 0x07
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#define DAVINCI_I2C_IVR_SCD 0x06
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#define DAVINCI_I2C_IVR_XRDY 0x05
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#define DAVINCI_I2C_IVR_RDR 0x04
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#define DAVINCI_I2C_IVR_ARDY 0x03
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#define DAVINCI_I2C_IVR_NACK 0x02
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#define DAVINCI_I2C_IVR_AL 0x01
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#define DAVINCI_I2C_STR_BB BIT(12)
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#define DAVINCI_I2C_STR_RSFULL BIT(11)
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#define DAVINCI_I2C_STR_SCD BIT(5)
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#define DAVINCI_I2C_STR_ARDY BIT(2)
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#define DAVINCI_I2C_STR_NACK BIT(1)
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#define DAVINCI_I2C_STR_AL BIT(0)
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#define DAVINCI_I2C_MDR_NACK BIT(15)
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#define DAVINCI_I2C_MDR_STT BIT(13)
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#define DAVINCI_I2C_MDR_STP BIT(11)
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#define DAVINCI_I2C_MDR_MST BIT(10)
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#define DAVINCI_I2C_MDR_TRX BIT(9)
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#define DAVINCI_I2C_MDR_XA BIT(8)
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#define DAVINCI_I2C_MDR_RM BIT(7)
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#define DAVINCI_I2C_MDR_IRS BIT(5)
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#define DAVINCI_I2C_IMR_AAS BIT(6)
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#define DAVINCI_I2C_IMR_SCD BIT(5)
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#define DAVINCI_I2C_IMR_XRDY BIT(4)
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#define DAVINCI_I2C_IMR_RRDY BIT(3)
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#define DAVINCI_I2C_IMR_ARDY BIT(2)
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#define DAVINCI_I2C_IMR_NACK BIT(1)
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#define DAVINCI_I2C_IMR_AL BIT(0)
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/* set SDA and SCL as GPIO */
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#define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
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/* set SCL as output when used as GPIO*/
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#define DAVINCI_I2C_DIR_PDIR0 BIT(0)
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/* set SDA as output when used as GPIO*/
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#define DAVINCI_I2C_DIR_PDIR1 BIT(1)
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/* read SCL GPIO level */
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#define DAVINCI_I2C_DIN_PDIN0 BIT(0)
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/* read SDA GPIO level */
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#define DAVINCI_I2C_DIN_PDIN1 BIT(1)
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/*set the SCL GPIO high */
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#define DAVINCI_I2C_DSET_PDSET0 BIT(0)
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/*set the SDA GPIO high */
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#define DAVINCI_I2C_DSET_PDSET1 BIT(1)
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/* set the SCL GPIO low */
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#define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
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/* set the SDA GPIO low */
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#define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
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struct davinci_i2c_dev {
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struct device *dev;
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void __iomem *base;
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struct completion cmd_complete;
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struct clk *clk;
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int cmd_err;
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u8 *buf;
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size_t buf_len;
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int irq;
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int stop;
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u8 terminate;
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struct i2c_adapter adapter;
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#ifdef CONFIG_CPU_FREQ
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struct completion xfr_complete;
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struct notifier_block freq_transition;
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#endif
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struct davinci_i2c_platform_data *pdata;
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};
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/* default platform data to use if not supplied in the platform_device */
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static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
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.bus_freq = 100,
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.bus_delay = 0,
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};
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static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
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int reg, u16 val)
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{
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writew_relaxed(val, i2c_dev->base + reg);
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}
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static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
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{
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return readw_relaxed(i2c_dev->base + reg);
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}
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static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
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int val)
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{
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u16 w;
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w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
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if (!val) /* put I2C into reset */
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w &= ~DAVINCI_I2C_MDR_IRS;
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else /* take I2C out of reset */
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w |= DAVINCI_I2C_MDR_IRS;
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davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
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}
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static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
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{
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struct davinci_i2c_platform_data *pdata = dev->pdata;
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u16 psc;
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u32 clk;
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u32 d;
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u32 clkh;
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u32 clkl;
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u32 input_clock = clk_get_rate(dev->clk);
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struct device_node *of_node = dev->dev->of_node;
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/* NOTE: I2C Clock divider programming info
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* As per I2C specs the following formulas provide prescaler
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* and low/high divider values
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* input clk --> PSC Div -----------> ICCL/H Div --> output clock
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* module clk
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*
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* output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
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*
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* Thus,
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* (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
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*
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* where if PSC == 0, d = 7,
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* if PSC == 1, d = 6
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* if PSC > 1 , d = 5
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*
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* Note:
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* d is always 6 on Keystone I2C controller
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*/
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/*
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* Both Davinci and current Keystone User Guides recommend a value
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* between 7MHz and 12MHz. In reality 7MHz module clock doesn't
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* always produce enough margin between SDA and SCL transitions.
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* Measurements show that the higher the module clock is, the
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* bigger is the margin, providing more reliable communication.
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* So we better target for 12MHz.
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*/
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psc = (input_clock / 12000000) - 1;
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if ((input_clock / (psc + 1)) > 12000000)
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psc++; /* better to run under spec than over */
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d = (psc >= 2) ? 5 : 7 - psc;
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if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
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d = 6;
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clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
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/* Avoid driving the bus too fast because of rounding errors above */
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if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
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clk++;
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/*
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* According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
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* least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
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* to LOW ratio as 1 to 2 is more safe.
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*/
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if (pdata->bus_freq > 100)
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clkl = (clk << 1) / 3;
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else
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clkl = (clk >> 1);
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/*
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* It's not always possible to have 1 to 2 ratio when d=7, so fall back
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* to minimal possible clkh in this case.
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*/
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if (clk >= clkl + d) {
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clkh = clk - clkl - d;
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clkl -= d;
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} else {
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clkh = 0;
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clkl = clk - (d << 1);
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}
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davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
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davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
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davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
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dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
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}
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/*
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* This function configures I2C and brings I2C out of reset.
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* This function is called during I2C init function. This function
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* also gets called if I2C encounters any errors.
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*/
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static int i2c_davinci_init(struct davinci_i2c_dev *dev)
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{
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struct davinci_i2c_platform_data *pdata = dev->pdata;
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/* put I2C into reset */
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davinci_i2c_reset_ctrl(dev, 0);
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/* compute clock dividers */
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i2c_davinci_calc_clk_dividers(dev);
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/* Respond at reserved "SMBus Host" slave address" (and zero);
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* we seem to have no option to not respond...
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*/
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davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
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dev_dbg(dev->dev, "PSC = %d\n",
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davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
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dev_dbg(dev->dev, "CLKL = %d\n",
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davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
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dev_dbg(dev->dev, "CLKH = %d\n",
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davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
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dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
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pdata->bus_freq, pdata->bus_delay);
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/* Take the I2C module out of reset: */
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davinci_i2c_reset_ctrl(dev, 1);
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/* Enable interrupts */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
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return 0;
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}
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/*
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* This routine does i2c bus recovery by using i2c_generic_gpio_recovery
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* which is provided by I2C Bus recovery infrastructure.
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*/
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static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
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{
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struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
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/* Disable interrupts */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
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/* put I2C into reset */
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davinci_i2c_reset_ctrl(dev, 0);
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}
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static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
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{
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struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
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i2c_davinci_init(dev);
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}
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static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
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.recover_bus = i2c_generic_gpio_recovery,
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.prepare_recovery = davinci_i2c_prepare_recovery,
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.unprepare_recovery = davinci_i2c_unprepare_recovery,
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};
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static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
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{
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struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
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if (val)
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davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
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DAVINCI_I2C_DSET_PDSET0);
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else
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davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
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DAVINCI_I2C_DCLR_PDCLR0);
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}
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static int davinci_i2c_get_scl(struct i2c_adapter *adap)
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{
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struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
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int val;
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/* read the state of SCL */
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val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
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return val & DAVINCI_I2C_DIN_PDIN0;
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}
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static int davinci_i2c_get_sda(struct i2c_adapter *adap)
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{
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struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
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int val;
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/* read the state of SDA */
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val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
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return val & DAVINCI_I2C_DIN_PDIN1;
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}
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static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
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{
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struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
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davinci_i2c_prepare_recovery(adap);
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/* SCL output, SDA input */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
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/* change to GPIO mode */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
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DAVINCI_I2C_FUNC_PFUNC0);
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}
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static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
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{
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struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
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/* change back to I2C mode */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
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davinci_i2c_unprepare_recovery(adap);
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}
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static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
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.recover_bus = i2c_generic_scl_recovery,
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.set_scl = davinci_i2c_set_scl,
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.get_scl = davinci_i2c_get_scl,
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.get_sda = davinci_i2c_get_sda,
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.prepare_recovery = davinci_i2c_scl_prepare_recovery,
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.unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
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};
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/*
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* Waiting for bus not busy
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*/
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static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
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{
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unsigned long timeout = jiffies + dev->adapter.timeout;
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do {
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if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
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return 0;
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schedule_timeout_uninterruptible(1);
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} while (time_before_eq(jiffies, timeout));
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dev_warn(dev->dev, "timeout waiting for bus ready\n");
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i2c_recover_bus(&dev->adapter);
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/*
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* if bus is still "busy" here, it's most probably a HW problem like
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* short-circuit
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*/
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if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
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return -EIO;
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return 0;
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}
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/*
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* Low level master read/write transaction. This function is called
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* from i2c_davinci_xfer.
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*/
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static int
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i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
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{
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struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
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struct davinci_i2c_platform_data *pdata = dev->pdata;
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u32 flag;
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u16 w;
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unsigned long time_left;
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if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
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dev_warn(dev->dev, "transfer to own address aborted\n");
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return -EADDRNOTAVAIL;
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}
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/* Introduce a delay, required for some boards (e.g Davinci EVM) */
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if (pdata->bus_delay)
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udelay(pdata->bus_delay);
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/* set the slave address */
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
|
|
|
|
dev->buf = msg->buf;
|
|
dev->buf_len = msg->len;
|
|
dev->stop = stop;
|
|
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
|
|
|
|
reinit_completion(&dev->cmd_complete);
|
|
dev->cmd_err = 0;
|
|
|
|
/* Take I2C out of reset and configure it as master */
|
|
flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
|
|
|
|
/* if the slave address is ten bit address, enable XA bit */
|
|
if (msg->flags & I2C_M_TEN)
|
|
flag |= DAVINCI_I2C_MDR_XA;
|
|
if (!(msg->flags & I2C_M_RD))
|
|
flag |= DAVINCI_I2C_MDR_TRX;
|
|
if (msg->len == 0)
|
|
flag |= DAVINCI_I2C_MDR_RM;
|
|
|
|
/* Enable receive or transmit interrupts */
|
|
w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
|
|
if (msg->flags & I2C_M_RD)
|
|
w |= DAVINCI_I2C_IMR_RRDY;
|
|
else
|
|
w |= DAVINCI_I2C_IMR_XRDY;
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
|
|
|
|
dev->terminate = 0;
|
|
|
|
/*
|
|
* Write mode register first as needed for correct behaviour
|
|
* on OMAP-L138, but don't set STT yet to avoid a race with XRDY
|
|
* occurring before we have loaded DXR
|
|
*/
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
|
|
|
|
/*
|
|
* First byte should be set here, not after interrupt,
|
|
* because transmit-data-ready interrupt can come before
|
|
* NACK-interrupt during sending of previous message and
|
|
* ICDXR may have wrong data
|
|
* It also saves us one interrupt, slightly faster
|
|
*/
|
|
if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
|
|
dev->buf_len--;
|
|
}
|
|
|
|
/* Set STT to begin transmit now DXR is loaded */
|
|
flag |= DAVINCI_I2C_MDR_STT;
|
|
if (stop && msg->len != 0)
|
|
flag |= DAVINCI_I2C_MDR_STP;
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
|
|
|
|
time_left = wait_for_completion_timeout(&dev->cmd_complete,
|
|
dev->adapter.timeout);
|
|
if (!time_left) {
|
|
dev_err(dev->dev, "controller timed out\n");
|
|
i2c_recover_bus(adap);
|
|
dev->buf_len = 0;
|
|
return -ETIMEDOUT;
|
|
}
|
|
if (dev->buf_len) {
|
|
/* This should be 0 if all bytes were transferred
|
|
* or dev->cmd_err denotes an error.
|
|
*/
|
|
dev_err(dev->dev, "abnormal termination buf_len=%i\n",
|
|
dev->buf_len);
|
|
dev->terminate = 1;
|
|
wmb();
|
|
dev->buf_len = 0;
|
|
return -EREMOTEIO;
|
|
}
|
|
|
|
/* no error */
|
|
if (likely(!dev->cmd_err))
|
|
return msg->len;
|
|
|
|
/* We have an error */
|
|
if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
|
|
i2c_davinci_init(dev);
|
|
return -EIO;
|
|
}
|
|
|
|
if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
|
|
if (msg->flags & I2C_M_IGNORE_NAK)
|
|
return msg->len;
|
|
w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
|
|
w |= DAVINCI_I2C_MDR_STP;
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
|
|
return -EREMOTEIO;
|
|
}
|
|
return -EIO;
|
|
}
|
|
|
|
/*
|
|
* Prepare controller for a transaction and call i2c_davinci_xfer_msg
|
|
*/
|
|
static int
|
|
i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
|
|
{
|
|
struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
int i;
|
|
int ret;
|
|
|
|
dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
|
|
|
|
ret = i2c_davinci_wait_bus_not_busy(dev);
|
|
if (ret < 0) {
|
|
dev_warn(dev->dev, "timeout waiting for bus ready\n");
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < num; i++) {
|
|
ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
|
|
dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
|
|
ret);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
complete(&dev->xfr_complete);
|
|
#endif
|
|
|
|
return num;
|
|
}
|
|
|
|
static u32 i2c_davinci_func(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
}
|
|
|
|
static void terminate_read(struct davinci_i2c_dev *dev)
|
|
{
|
|
u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
|
|
w |= DAVINCI_I2C_MDR_NACK;
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
|
|
|
|
/* Throw away data */
|
|
davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
|
|
if (!dev->terminate)
|
|
dev_err(dev->dev, "RDR IRQ while no data requested\n");
|
|
}
|
|
static void terminate_write(struct davinci_i2c_dev *dev)
|
|
{
|
|
u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
|
|
w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
|
|
|
|
if (!dev->terminate)
|
|
dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
|
|
}
|
|
|
|
/*
|
|
* Interrupt service routine. This gets called whenever an I2C interrupt
|
|
* occurs.
|
|
*/
|
|
static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
|
|
{
|
|
struct davinci_i2c_dev *dev = dev_id;
|
|
u32 stat;
|
|
int count = 0;
|
|
u16 w;
|
|
|
|
while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
|
|
dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
|
|
if (count++ == 100) {
|
|
dev_warn(dev->dev, "Too much work in one IRQ\n");
|
|
break;
|
|
}
|
|
|
|
switch (stat) {
|
|
case DAVINCI_I2C_IVR_AL:
|
|
/* Arbitration lost, must retry */
|
|
dev->cmd_err |= DAVINCI_I2C_STR_AL;
|
|
dev->buf_len = 0;
|
|
complete(&dev->cmd_complete);
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_NACK:
|
|
dev->cmd_err |= DAVINCI_I2C_STR_NACK;
|
|
dev->buf_len = 0;
|
|
complete(&dev->cmd_complete);
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_ARDY:
|
|
davinci_i2c_write_reg(dev,
|
|
DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
|
|
if (((dev->buf_len == 0) && (dev->stop != 0)) ||
|
|
(dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
|
|
w = davinci_i2c_read_reg(dev,
|
|
DAVINCI_I2C_MDR_REG);
|
|
w |= DAVINCI_I2C_MDR_STP;
|
|
davinci_i2c_write_reg(dev,
|
|
DAVINCI_I2C_MDR_REG, w);
|
|
}
|
|
complete(&dev->cmd_complete);
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_RDR:
|
|
if (dev->buf_len) {
|
|
*dev->buf++ =
|
|
davinci_i2c_read_reg(dev,
|
|
DAVINCI_I2C_DRR_REG);
|
|
dev->buf_len--;
|
|
if (dev->buf_len)
|
|
continue;
|
|
|
|
davinci_i2c_write_reg(dev,
|
|
DAVINCI_I2C_STR_REG,
|
|
DAVINCI_I2C_IMR_RRDY);
|
|
} else {
|
|
/* signal can terminate transfer */
|
|
terminate_read(dev);
|
|
}
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_XRDY:
|
|
if (dev->buf_len) {
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
|
|
*dev->buf++);
|
|
dev->buf_len--;
|
|
if (dev->buf_len)
|
|
continue;
|
|
|
|
w = davinci_i2c_read_reg(dev,
|
|
DAVINCI_I2C_IMR_REG);
|
|
w &= ~DAVINCI_I2C_IMR_XRDY;
|
|
davinci_i2c_write_reg(dev,
|
|
DAVINCI_I2C_IMR_REG,
|
|
w);
|
|
} else {
|
|
/* signal can terminate transfer */
|
|
terminate_write(dev);
|
|
}
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_SCD:
|
|
davinci_i2c_write_reg(dev,
|
|
DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
|
|
complete(&dev->cmd_complete);
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_AAS:
|
|
dev_dbg(dev->dev, "Address as slave interrupt\n");
|
|
break;
|
|
|
|
default:
|
|
dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return count ? IRQ_HANDLED : IRQ_NONE;
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
|
|
unsigned long val, void *data)
|
|
{
|
|
struct davinci_i2c_dev *dev;
|
|
|
|
dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
|
|
if (val == CPUFREQ_PRECHANGE) {
|
|
wait_for_completion(&dev->xfr_complete);
|
|
davinci_i2c_reset_ctrl(dev, 0);
|
|
} else if (val == CPUFREQ_POSTCHANGE) {
|
|
i2c_davinci_calc_clk_dividers(dev);
|
|
davinci_i2c_reset_ctrl(dev, 1);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
|
|
{
|
|
dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
|
|
|
|
return cpufreq_register_notifier(&dev->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
|
|
static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
|
|
{
|
|
cpufreq_unregister_notifier(&dev->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
#else
|
|
static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
static struct i2c_algorithm i2c_davinci_algo = {
|
|
.master_xfer = i2c_davinci_xfer,
|
|
.functionality = i2c_davinci_func,
|
|
};
|
|
|
|
static const struct of_device_id davinci_i2c_of_match[] = {
|
|
{.compatible = "ti,davinci-i2c", },
|
|
{.compatible = "ti,keystone-i2c", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
|
|
|
|
static int davinci_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
struct davinci_i2c_dev *dev;
|
|
struct i2c_adapter *adap;
|
|
struct resource *mem;
|
|
int r, irq;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq <= 0) {
|
|
if (!irq)
|
|
irq = -ENXIO;
|
|
if (irq != -EPROBE_DEFER)
|
|
dev_err(&pdev->dev,
|
|
"can't get irq resource ret=%d\n", irq);
|
|
return irq;
|
|
}
|
|
|
|
dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
|
|
GFP_KERNEL);
|
|
if (!dev) {
|
|
dev_err(&pdev->dev, "Memory allocation failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
init_completion(&dev->cmd_complete);
|
|
#ifdef CONFIG_CPU_FREQ
|
|
init_completion(&dev->xfr_complete);
|
|
#endif
|
|
dev->dev = &pdev->dev;
|
|
dev->irq = irq;
|
|
dev->pdata = dev_get_platdata(&pdev->dev);
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
if (!dev->pdata && pdev->dev.of_node) {
|
|
u32 prop;
|
|
|
|
dev->pdata = devm_kzalloc(&pdev->dev,
|
|
sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
|
|
if (!dev->pdata)
|
|
return -ENOMEM;
|
|
|
|
memcpy(dev->pdata, &davinci_i2c_platform_data_default,
|
|
sizeof(struct davinci_i2c_platform_data));
|
|
if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
|
|
&prop))
|
|
dev->pdata->bus_freq = prop / 1000;
|
|
|
|
dev->pdata->has_pfunc =
|
|
of_property_read_bool(pdev->dev.of_node,
|
|
"ti,has-pfunc");
|
|
} else if (!dev->pdata) {
|
|
dev->pdata = &davinci_i2c_platform_data_default;
|
|
}
|
|
|
|
dev->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(dev->clk))
|
|
return -ENODEV;
|
|
clk_prepare_enable(dev->clk);
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
dev->base = devm_ioremap_resource(&pdev->dev, mem);
|
|
if (IS_ERR(dev->base)) {
|
|
r = PTR_ERR(dev->base);
|
|
goto err_unuse_clocks;
|
|
}
|
|
|
|
i2c_davinci_init(dev);
|
|
|
|
r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
|
|
pdev->name, dev);
|
|
if (r) {
|
|
dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
|
|
goto err_unuse_clocks;
|
|
}
|
|
|
|
r = i2c_davinci_cpufreq_register(dev);
|
|
if (r) {
|
|
dev_err(&pdev->dev, "failed to register cpufreq\n");
|
|
goto err_unuse_clocks;
|
|
}
|
|
|
|
adap = &dev->adapter;
|
|
i2c_set_adapdata(adap, dev);
|
|
adap->owner = THIS_MODULE;
|
|
adap->class = I2C_CLASS_DEPRECATED;
|
|
strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
|
|
adap->algo = &i2c_davinci_algo;
|
|
adap->dev.parent = &pdev->dev;
|
|
adap->timeout = DAVINCI_I2C_TIMEOUT;
|
|
adap->dev.of_node = pdev->dev.of_node;
|
|
|
|
if (dev->pdata->has_pfunc)
|
|
adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
|
|
else if (dev->pdata->scl_pin) {
|
|
adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info;
|
|
adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin;
|
|
adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin;
|
|
}
|
|
|
|
adap->nr = pdev->id;
|
|
r = i2c_add_numbered_adapter(adap);
|
|
if (r)
|
|
goto err_unuse_clocks;
|
|
|
|
return 0;
|
|
|
|
err_unuse_clocks:
|
|
clk_disable_unprepare(dev->clk);
|
|
dev->clk = NULL;
|
|
return r;
|
|
}
|
|
|
|
static int davinci_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
|
|
|
|
i2c_davinci_cpufreq_deregister(dev);
|
|
|
|
i2c_del_adapter(&dev->adapter);
|
|
|
|
clk_disable_unprepare(dev->clk);
|
|
dev->clk = NULL;
|
|
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int davinci_i2c_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
|
|
|
|
/* put I2C into reset */
|
|
davinci_i2c_reset_ctrl(i2c_dev, 0);
|
|
clk_disable_unprepare(i2c_dev->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int davinci_i2c_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
|
|
|
|
clk_prepare_enable(i2c_dev->clk);
|
|
/* take I2C out of reset */
|
|
davinci_i2c_reset_ctrl(i2c_dev, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops davinci_i2c_pm = {
|
|
.suspend = davinci_i2c_suspend,
|
|
.resume = davinci_i2c_resume,
|
|
};
|
|
|
|
#define davinci_i2c_pm_ops (&davinci_i2c_pm)
|
|
#else
|
|
#define davinci_i2c_pm_ops NULL
|
|
#endif
|
|
|
|
/* work with hotplug and coldplug */
|
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MODULE_ALIAS("platform:i2c_davinci");
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|
|
|
static struct platform_driver davinci_i2c_driver = {
|
|
.probe = davinci_i2c_probe,
|
|
.remove = davinci_i2c_remove,
|
|
.driver = {
|
|
.name = "i2c_davinci",
|
|
.pm = davinci_i2c_pm_ops,
|
|
.of_match_table = davinci_i2c_of_match,
|
|
},
|
|
};
|
|
|
|
/* I2C may be needed to bring up other drivers */
|
|
static int __init davinci_i2c_init_driver(void)
|
|
{
|
|
return platform_driver_register(&davinci_i2c_driver);
|
|
}
|
|
subsys_initcall(davinci_i2c_init_driver);
|
|
|
|
static void __exit davinci_i2c_exit_driver(void)
|
|
{
|
|
platform_driver_unregister(&davinci_i2c_driver);
|
|
}
|
|
module_exit(davinci_i2c_exit_driver);
|
|
|
|
MODULE_AUTHOR("Texas Instruments India");
|
|
MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
|
|
MODULE_LICENSE("GPL");
|