1091 строка
26 KiB
C
1091 строка
26 KiB
C
/*
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* Copyright 2013 Emilio López
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*
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* Emilio López <emilio@elopez.com.ar>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk-factors.h"
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static DEFINE_SPINLOCK(clk_lock);
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/* Maximum number of parents our clocks have */
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#define SUNXI_MAX_PARENTS 5
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/**
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* sun4i_osc_clk_setup() - Setup function for gatable oscillator
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*/
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#define SUNXI_OSC24M_GATE 0
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static void __init sun4i_osc_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_fixed_rate *fixed;
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struct clk_gate *gate;
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const char *clk_name = node->name;
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u32 rate;
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if (of_property_read_u32(node, "clock-frequency", &rate))
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return;
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/* allocate fixed-rate and gate clock structs */
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fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
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if (!fixed)
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return;
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate)
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goto err_free_fixed;
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/* set up gate and fixed rate properties */
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gate->reg = of_iomap(node, 0);
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gate->bit_idx = SUNXI_OSC24M_GATE;
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gate->lock = &clk_lock;
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fixed->fixed_rate = rate;
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clk = clk_register_composite(NULL, clk_name,
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NULL, 0,
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NULL, NULL,
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&fixed->hw, &clk_fixed_rate_ops,
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&gate->hw, &clk_gate_ops,
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CLK_IS_ROOT);
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if (IS_ERR(clk))
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goto err_free_gate;
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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return;
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err_free_gate:
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kfree(gate);
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err_free_fixed:
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kfree(fixed);
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}
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CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
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/**
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* sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
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* PLL1 rate is calculated as follows
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* rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
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* parent_rate is always 24Mhz
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*/
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static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u8 div;
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/* Normalize value to a 6M multiple */
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div = *freq / 6000000;
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*freq = 6000000 * div;
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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/* m is always zero for pll1 */
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*m = 0;
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/* k is 1 only on these cases */
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if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
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*k = 1;
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else
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*k = 0;
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/* p will be 3 for divs under 10 */
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if (div < 10)
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*p = 3;
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/* p will be 2 for divs between 10 - 20 and odd divs under 32 */
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else if (div < 20 || (div < 32 && (div & 1)))
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*p = 2;
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/* p will be 1 for even divs under 32, divs under 40 and odd pairs
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* of divs between 40-62 */
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else if (div < 40 || (div < 64 && (div & 2)))
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*p = 1;
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/* any other entries have p = 0 */
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else
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*p = 0;
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/* calculate a suitable n based on k and p */
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div <<= *p;
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div /= (*k + 1);
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*n = div / 4;
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}
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/**
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* sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
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* PLL1 rate is calculated as follows
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* rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
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* parent_rate should always be 24MHz
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*/
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static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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/*
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* We can operate only on MHz, this will make our life easier
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* later.
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*/
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u32 freq_mhz = *freq / 1000000;
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u32 parent_freq_mhz = parent_rate / 1000000;
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/*
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* Round down the frequency to the closest multiple of either
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* 6 or 16
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*/
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u32 round_freq_6 = round_down(freq_mhz, 6);
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u32 round_freq_16 = round_down(freq_mhz, 16);
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if (round_freq_6 > round_freq_16)
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freq_mhz = round_freq_6;
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else
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freq_mhz = round_freq_16;
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*freq = freq_mhz * 1000000;
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/*
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* If the factors pointer are null, we were just called to
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* round down the frequency.
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* Exit.
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*/
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if (n == NULL)
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return;
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/* If the frequency is a multiple of 32 MHz, k is always 3 */
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if (!(freq_mhz % 32))
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*k = 3;
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/* If the frequency is a multiple of 9 MHz, k is always 2 */
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else if (!(freq_mhz % 9))
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*k = 2;
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/* If the frequency is a multiple of 8 MHz, k is always 1 */
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else if (!(freq_mhz % 8))
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*k = 1;
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/* Otherwise, we don't use the k factor */
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else
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*k = 0;
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/*
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* If the frequency is a multiple of 2 but not a multiple of
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* 3, m is 3. This is the first time we use 6 here, yet we
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* will use it on several other places.
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* We use this number because it's the lowest frequency we can
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* generate (with n = 0, k = 0, m = 3), so every other frequency
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* somehow relates to this frequency.
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*/
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if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
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*m = 2;
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/*
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* If the frequency is a multiple of 6MHz, but the factor is
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* odd, m will be 3
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*/
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else if ((freq_mhz / 6) & 1)
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*m = 3;
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/* Otherwise, we end up with m = 1 */
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else
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*m = 1;
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/* Calculate n thanks to the above factors we already got */
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*n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
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/*
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* If n end up being outbound, and that we can still decrease
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* m, do it.
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*/
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if ((*n + 1) > 31 && (*m + 1) > 1) {
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*n = (*n + 1) / 2 - 1;
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*m = (*m + 1) / 2 - 1;
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}
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}
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/**
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* sun4i_get_pll5_factors() - calculates n, k factors for PLL5
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* PLL5 rate is calculated as follows
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* rate = parent_rate * n * (k + 1)
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* parent_rate is always 24Mhz
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*/
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static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u8 div;
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/* Normalize value to a parent_rate multiple (24M) */
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div = *freq / parent_rate;
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*freq = parent_rate * div;
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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if (div < 31)
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*k = 0;
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else if (div / 2 < 31)
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*k = 1;
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else if (div / 3 < 31)
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*k = 2;
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else
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*k = 3;
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*n = DIV_ROUND_UP(div, (*k+1));
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}
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/**
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* sun4i_get_apb1_factors() - calculates m, p factors for APB1
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* APB1 rate is calculated as follows
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* rate = (parent_rate >> p) / (m + 1);
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*/
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static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u8 calcm, calcp;
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if (parent_rate < *freq)
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*freq = parent_rate;
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parent_rate = (parent_rate + (*freq - 1)) / *freq;
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/* Invalid rate! */
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if (parent_rate > 32)
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return;
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if (parent_rate <= 4)
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calcp = 0;
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else if (parent_rate <= 8)
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calcp = 1;
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else if (parent_rate <= 16)
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calcp = 2;
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else
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calcp = 3;
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calcm = (parent_rate >> calcp) - 1;
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*freq = (parent_rate >> calcp) / (calcm + 1);
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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*m = calcm;
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*p = calcp;
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}
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/**
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* sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
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* MMC rate is calculated as follows
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* rate = (parent_rate >> p) / (m + 1);
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*/
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static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u8 div, calcm, calcp;
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/* These clocks can only divide, so we will never be able to achieve
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* frequencies higher than the parent frequency */
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if (*freq > parent_rate)
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*freq = parent_rate;
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div = parent_rate / *freq;
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if (div < 16)
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calcp = 0;
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else if (div / 2 < 16)
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calcp = 1;
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else if (div / 4 < 16)
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calcp = 2;
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else
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calcp = 3;
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calcm = DIV_ROUND_UP(div, 1 << calcp);
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*freq = (parent_rate >> calcp) / calcm;
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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*m = calcm - 1;
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*p = calcp;
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}
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/**
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* sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
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* CLK_OUT rate is calculated as follows
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* rate = (parent_rate >> p) / (m + 1);
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*/
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static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u8 div, calcm, calcp;
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/* These clocks can only divide, so we will never be able to achieve
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* frequencies higher than the parent frequency */
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if (*freq > parent_rate)
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*freq = parent_rate;
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div = parent_rate / *freq;
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if (div < 32)
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calcp = 0;
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else if (div / 2 < 32)
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calcp = 1;
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else if (div / 4 < 32)
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calcp = 2;
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else
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calcp = 3;
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calcm = DIV_ROUND_UP(div, 1 << calcp);
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*freq = (parent_rate >> calcp) / calcm;
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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*m = calcm - 1;
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*p = calcp;
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}
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/**
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* sunxi_factors_clk_setup() - Setup function for factor clocks
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*/
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#define SUNXI_FACTORS_MUX_MASK 0x3
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struct factors_data {
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int enable;
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int mux;
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struct clk_factors_config *table;
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void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
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};
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static struct clk_factors_config sun4i_pll1_config = {
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.nshift = 8,
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.nwidth = 5,
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.kshift = 4,
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.kwidth = 2,
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.mshift = 0,
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.mwidth = 2,
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.pshift = 16,
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.pwidth = 2,
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};
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static struct clk_factors_config sun6i_a31_pll1_config = {
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.nshift = 8,
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.nwidth = 5,
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.kshift = 4,
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.kwidth = 2,
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.mshift = 0,
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.mwidth = 2,
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};
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static struct clk_factors_config sun4i_pll5_config = {
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.nshift = 8,
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.nwidth = 5,
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.kshift = 4,
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.kwidth = 2,
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};
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static struct clk_factors_config sun4i_apb1_config = {
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.mshift = 0,
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.mwidth = 5,
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.pshift = 16,
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.pwidth = 2,
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};
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/* user manual says "n" but it's really "p" */
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static struct clk_factors_config sun4i_mod0_config = {
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.mshift = 0,
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.mwidth = 4,
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.pshift = 16,
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.pwidth = 2,
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};
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/* user manual says "n" but it's really "p" */
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static struct clk_factors_config sun7i_a20_out_config = {
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.mshift = 8,
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.mwidth = 5,
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.pshift = 20,
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.pwidth = 2,
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};
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static const struct factors_data sun4i_pll1_data __initconst = {
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.enable = 31,
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.table = &sun4i_pll1_config,
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.getter = sun4i_get_pll1_factors,
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};
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static const struct factors_data sun6i_a31_pll1_data __initconst = {
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.enable = 31,
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.table = &sun6i_a31_pll1_config,
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.getter = sun6i_a31_get_pll1_factors,
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};
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static const struct factors_data sun4i_pll5_data __initconst = {
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.enable = 31,
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.table = &sun4i_pll5_config,
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.getter = sun4i_get_pll5_factors,
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};
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static const struct factors_data sun4i_apb1_data __initconst = {
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.table = &sun4i_apb1_config,
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.getter = sun4i_get_apb1_factors,
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};
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static const struct factors_data sun4i_mod0_data __initconst = {
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.enable = 31,
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.mux = 24,
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.table = &sun4i_mod0_config,
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.getter = sun4i_get_mod0_factors,
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};
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static const struct factors_data sun7i_a20_out_data __initconst = {
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.enable = 31,
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.mux = 24,
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.table = &sun7i_a20_out_config,
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.getter = sun7i_a20_get_out_factors,
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};
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static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
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const struct factors_data *data)
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{
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struct clk *clk;
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struct clk_factors *factors;
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struct clk_gate *gate = NULL;
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struct clk_mux *mux = NULL;
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struct clk_hw *gate_hw = NULL;
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struct clk_hw *mux_hw = NULL;
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const char *clk_name = node->name;
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const char *parents[SUNXI_MAX_PARENTS];
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void *reg;
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int i = 0;
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reg = of_iomap(node, 0);
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/* if we have a mux, we will have >1 parents */
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while (i < SUNXI_MAX_PARENTS &&
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(parents[i] = of_clk_get_parent_name(node, i)) != NULL)
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i++;
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/* Nodes should be providing the name via clock-output-names
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* but originally our dts didn't, and so we used node->name.
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* The new, better nodes look like clk@deadbeef, so we pull the
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* name just in this case */
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if (!strcmp("clk", clk_name)) {
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of_property_read_string_index(node, "clock-output-names",
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0, &clk_name);
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}
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factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
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if (!factors)
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return NULL;
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/* Add a gate if this factor clock can be gated */
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if (data->enable) {
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate) {
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kfree(factors);
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return NULL;
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}
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/* set up gate properties */
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gate->reg = reg;
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gate->bit_idx = data->enable;
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gate->lock = &clk_lock;
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gate_hw = &gate->hw;
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}
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/* Add a mux if this factor clock can be muxed */
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if (data->mux) {
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mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
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if (!mux) {
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kfree(factors);
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kfree(gate);
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return NULL;
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}
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/* set up gate properties */
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mux->reg = reg;
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mux->shift = data->mux;
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mux->mask = SUNXI_FACTORS_MUX_MASK;
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mux->lock = &clk_lock;
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mux_hw = &mux->hw;
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}
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/* set up factors properties */
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factors->reg = reg;
|
|
factors->config = data->table;
|
|
factors->get_factors = data->getter;
|
|
factors->lock = &clk_lock;
|
|
|
|
clk = clk_register_composite(NULL, clk_name,
|
|
parents, i,
|
|
mux_hw, &clk_mux_ops,
|
|
&factors->hw, &clk_factors_ops,
|
|
gate_hw, &clk_gate_ops, 0);
|
|
|
|
if (!IS_ERR(clk)) {
|
|
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
|
clk_register_clkdev(clk, clk_name, NULL);
|
|
}
|
|
|
|
return clk;
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
* sunxi_mux_clk_setup() - Setup function for muxes
|
|
*/
|
|
|
|
#define SUNXI_MUX_GATE_WIDTH 2
|
|
|
|
struct mux_data {
|
|
u8 shift;
|
|
};
|
|
|
|
static const struct mux_data sun4i_cpu_mux_data __initconst = {
|
|
.shift = 16,
|
|
};
|
|
|
|
static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
|
|
.shift = 12,
|
|
};
|
|
|
|
static const struct mux_data sun4i_apb1_mux_data __initconst = {
|
|
.shift = 24,
|
|
};
|
|
|
|
static void __init sunxi_mux_clk_setup(struct device_node *node,
|
|
struct mux_data *data)
|
|
{
|
|
struct clk *clk;
|
|
const char *clk_name = node->name;
|
|
const char *parents[SUNXI_MAX_PARENTS];
|
|
void *reg;
|
|
int i = 0;
|
|
|
|
reg = of_iomap(node, 0);
|
|
|
|
while (i < SUNXI_MAX_PARENTS &&
|
|
(parents[i] = of_clk_get_parent_name(node, i)) != NULL)
|
|
i++;
|
|
|
|
clk = clk_register_mux(NULL, clk_name, parents, i,
|
|
CLK_SET_RATE_NO_REPARENT, reg,
|
|
data->shift, SUNXI_MUX_GATE_WIDTH,
|
|
0, &clk_lock);
|
|
|
|
if (clk) {
|
|
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
|
clk_register_clkdev(clk, clk_name, NULL);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
* sunxi_divider_clk_setup() - Setup function for simple divider clocks
|
|
*/
|
|
|
|
struct div_data {
|
|
u8 shift;
|
|
u8 pow;
|
|
u8 width;
|
|
};
|
|
|
|
static const struct div_data sun4i_axi_data __initconst = {
|
|
.shift = 0,
|
|
.pow = 0,
|
|
.width = 2,
|
|
};
|
|
|
|
static const struct div_data sun4i_ahb_data __initconst = {
|
|
.shift = 4,
|
|
.pow = 1,
|
|
.width = 2,
|
|
};
|
|
|
|
static const struct div_data sun4i_apb0_data __initconst = {
|
|
.shift = 8,
|
|
.pow = 1,
|
|
.width = 2,
|
|
};
|
|
|
|
static const struct div_data sun6i_a31_apb2_div_data __initconst = {
|
|
.shift = 0,
|
|
.pow = 0,
|
|
.width = 4,
|
|
};
|
|
|
|
static void __init sunxi_divider_clk_setup(struct device_node *node,
|
|
struct div_data *data)
|
|
{
|
|
struct clk *clk;
|
|
const char *clk_name = node->name;
|
|
const char *clk_parent;
|
|
void *reg;
|
|
|
|
reg = of_iomap(node, 0);
|
|
|
|
clk_parent = of_clk_get_parent_name(node, 0);
|
|
|
|
clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
|
|
reg, data->shift, data->width,
|
|
data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
|
|
&clk_lock);
|
|
if (clk) {
|
|
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
|
clk_register_clkdev(clk, clk_name, NULL);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
|
|
*/
|
|
|
|
#define SUNXI_GATES_MAX_SIZE 64
|
|
|
|
struct gates_data {
|
|
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
|
|
};
|
|
|
|
static const struct gates_data sun4i_axi_gates_data __initconst = {
|
|
.mask = {1},
|
|
};
|
|
|
|
static const struct gates_data sun4i_ahb_gates_data __initconst = {
|
|
.mask = {0x7F77FFF, 0x14FB3F},
|
|
};
|
|
|
|
static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
|
|
.mask = {0x147667e7, 0x185915},
|
|
};
|
|
|
|
static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
|
|
.mask = {0x107067e7, 0x185111},
|
|
};
|
|
|
|
static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
|
|
.mask = {0xEDFE7F62, 0x794F931},
|
|
};
|
|
|
|
static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
|
|
.mask = { 0x12f77fff, 0x16ff3f },
|
|
};
|
|
|
|
static const struct gates_data sun4i_apb0_gates_data __initconst = {
|
|
.mask = {0x4EF},
|
|
};
|
|
|
|
static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
|
|
.mask = {0x469},
|
|
};
|
|
|
|
static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
|
|
.mask = {0x61},
|
|
};
|
|
|
|
static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
|
|
.mask = { 0x4ff },
|
|
};
|
|
|
|
static const struct gates_data sun4i_apb1_gates_data __initconst = {
|
|
.mask = {0xFF00F7},
|
|
};
|
|
|
|
static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
|
|
.mask = {0xf0007},
|
|
};
|
|
|
|
static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
|
|
.mask = {0xa0007},
|
|
};
|
|
|
|
static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
|
|
.mask = {0x3031},
|
|
};
|
|
|
|
static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
|
|
.mask = {0x3F000F},
|
|
};
|
|
|
|
static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
|
|
.mask = { 0xff80ff },
|
|
};
|
|
|
|
static void __init sunxi_gates_clk_setup(struct device_node *node,
|
|
struct gates_data *data)
|
|
{
|
|
struct clk_onecell_data *clk_data;
|
|
const char *clk_parent;
|
|
const char *clk_name;
|
|
void *reg;
|
|
int qty;
|
|
int i = 0;
|
|
int j = 0;
|
|
int ignore;
|
|
|
|
reg = of_iomap(node, 0);
|
|
|
|
clk_parent = of_clk_get_parent_name(node, 0);
|
|
|
|
/* Worst-case size approximation and memory allocation */
|
|
qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
|
|
clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
|
|
if (!clk_data)
|
|
return;
|
|
clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
|
|
if (!clk_data->clks) {
|
|
kfree(clk_data);
|
|
return;
|
|
}
|
|
|
|
for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
|
|
of_property_read_string_index(node, "clock-output-names",
|
|
j, &clk_name);
|
|
|
|
/* No driver claims this clock, but it should remain gated */
|
|
ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
|
|
|
|
clk_data->clks[i] = clk_register_gate(NULL, clk_name,
|
|
clk_parent, ignore,
|
|
reg + 4 * (i/32), i % 32,
|
|
0, &clk_lock);
|
|
WARN_ON(IS_ERR(clk_data->clks[i]));
|
|
|
|
j++;
|
|
}
|
|
|
|
/* Adjust to the real max */
|
|
clk_data->clk_num = i;
|
|
|
|
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
* sunxi_divs_clk_setup() helper data
|
|
*/
|
|
|
|
#define SUNXI_DIVS_MAX_QTY 2
|
|
#define SUNXI_DIVISOR_WIDTH 2
|
|
|
|
struct divs_data {
|
|
const struct factors_data *factors; /* data for the factor clock */
|
|
struct {
|
|
u8 fixed; /* is it a fixed divisor? if not... */
|
|
struct clk_div_table *table; /* is it a table based divisor? */
|
|
u8 shift; /* otherwise it's a normal divisor with this shift */
|
|
u8 pow; /* is it power-of-two based? */
|
|
u8 gate; /* is it independently gateable? */
|
|
} div[SUNXI_DIVS_MAX_QTY];
|
|
};
|
|
|
|
static struct clk_div_table pll6_sata_tbl[] = {
|
|
{ .val = 0, .div = 6, },
|
|
{ .val = 1, .div = 12, },
|
|
{ .val = 2, .div = 18, },
|
|
{ .val = 3, .div = 24, },
|
|
{ } /* sentinel */
|
|
};
|
|
|
|
static const struct divs_data pll5_divs_data __initconst = {
|
|
.factors = &sun4i_pll5_data,
|
|
.div = {
|
|
{ .shift = 0, .pow = 0, }, /* M, DDR */
|
|
{ .shift = 16, .pow = 1, }, /* P, other */
|
|
}
|
|
};
|
|
|
|
static const struct divs_data pll6_divs_data __initconst = {
|
|
.factors = &sun4i_pll5_data,
|
|
.div = {
|
|
{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
|
|
{ .fixed = 2 }, /* P, other */
|
|
}
|
|
};
|
|
|
|
/**
|
|
* sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
|
|
*
|
|
* These clocks look something like this
|
|
* ________________________
|
|
* | ___divisor 1---|----> to consumer
|
|
* parent >--| pll___/___divisor 2---|----> to consumer
|
|
* | \_______________|____> to consumer
|
|
* |________________________|
|
|
*/
|
|
|
|
static void __init sunxi_divs_clk_setup(struct device_node *node,
|
|
struct divs_data *data)
|
|
{
|
|
struct clk_onecell_data *clk_data;
|
|
const char *parent = node->name;
|
|
const char *clk_name;
|
|
struct clk **clks, *pclk;
|
|
struct clk_hw *gate_hw, *rate_hw;
|
|
const struct clk_ops *rate_ops;
|
|
struct clk_gate *gate = NULL;
|
|
struct clk_fixed_factor *fix_factor;
|
|
struct clk_divider *divider;
|
|
void *reg;
|
|
int i = 0;
|
|
int flags, clkflags;
|
|
|
|
/* Set up factor clock that we will be dividing */
|
|
pclk = sunxi_factors_clk_setup(node, data->factors);
|
|
|
|
reg = of_iomap(node, 0);
|
|
|
|
clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
|
|
if (!clk_data)
|
|
return;
|
|
|
|
clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
|
|
if (!clks)
|
|
goto free_clkdata;
|
|
|
|
clk_data->clks = clks;
|
|
|
|
/* It's not a good idea to have automatic reparenting changing
|
|
* our RAM clock! */
|
|
clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
|
|
|
|
for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
|
|
if (of_property_read_string_index(node, "clock-output-names",
|
|
i, &clk_name) != 0)
|
|
break;
|
|
|
|
gate_hw = NULL;
|
|
rate_hw = NULL;
|
|
rate_ops = NULL;
|
|
|
|
/* If this leaf clock can be gated, create a gate */
|
|
if (data->div[i].gate) {
|
|
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
|
if (!gate)
|
|
goto free_clks;
|
|
|
|
gate->reg = reg;
|
|
gate->bit_idx = data->div[i].gate;
|
|
gate->lock = &clk_lock;
|
|
|
|
gate_hw = &gate->hw;
|
|
}
|
|
|
|
/* Leaves can be fixed or configurable divisors */
|
|
if (data->div[i].fixed) {
|
|
fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
|
|
if (!fix_factor)
|
|
goto free_gate;
|
|
|
|
fix_factor->mult = 1;
|
|
fix_factor->div = data->div[i].fixed;
|
|
|
|
rate_hw = &fix_factor->hw;
|
|
rate_ops = &clk_fixed_factor_ops;
|
|
} else {
|
|
divider = kzalloc(sizeof(*divider), GFP_KERNEL);
|
|
if (!divider)
|
|
goto free_gate;
|
|
|
|
flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
|
|
|
|
divider->reg = reg;
|
|
divider->shift = data->div[i].shift;
|
|
divider->width = SUNXI_DIVISOR_WIDTH;
|
|
divider->flags = flags;
|
|
divider->lock = &clk_lock;
|
|
divider->table = data->div[i].table;
|
|
|
|
rate_hw = ÷r->hw;
|
|
rate_ops = &clk_divider_ops;
|
|
}
|
|
|
|
/* Wrap the (potential) gate and the divisor on a composite
|
|
* clock to unify them */
|
|
clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
|
|
NULL, NULL,
|
|
rate_hw, rate_ops,
|
|
gate_hw, &clk_gate_ops,
|
|
clkflags);
|
|
|
|
WARN_ON(IS_ERR(clk_data->clks[i]));
|
|
clk_register_clkdev(clks[i], clk_name, NULL);
|
|
}
|
|
|
|
/* The last clock available on the getter is the parent */
|
|
clks[i++] = pclk;
|
|
|
|
/* Adjust to the real max */
|
|
clk_data->clk_num = i;
|
|
|
|
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
|
|
|
return;
|
|
|
|
free_gate:
|
|
kfree(gate);
|
|
free_clks:
|
|
kfree(clks);
|
|
free_clkdata:
|
|
kfree(clk_data);
|
|
}
|
|
|
|
|
|
|
|
/* Matches for factors clocks */
|
|
static const struct of_device_id clk_factors_match[] __initconst = {
|
|
{.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
|
|
{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
|
|
{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
|
|
{.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
|
|
{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
|
|
{}
|
|
};
|
|
|
|
/* Matches for divider clocks */
|
|
static const struct of_device_id clk_div_match[] __initconst = {
|
|
{.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,},
|
|
{.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,},
|
|
{.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,},
|
|
{.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
|
|
{}
|
|
};
|
|
|
|
/* Matches for divided outputs */
|
|
static const struct of_device_id clk_divs_match[] __initconst = {
|
|
{.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
|
|
{.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
|
|
{}
|
|
};
|
|
|
|
/* Matches for mux clocks */
|
|
static const struct of_device_id clk_mux_match[] __initconst = {
|
|
{.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
|
|
{.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
|
|
{.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
|
|
{}
|
|
};
|
|
|
|
/* Matches for gate clocks */
|
|
static const struct of_device_id clk_gates_match[] __initconst = {
|
|
{.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
|
|
{.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
|
|
{.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
|
|
{.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
|
|
{.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
|
|
{.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
|
|
{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
|
|
{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
|
|
{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
|
|
{.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
|
|
{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
|
|
{.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
|
|
{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
|
|
{.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
|
|
{.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
|
|
{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
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{}
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|
};
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|
|
|
static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
|
|
void *function)
|
|
{
|
|
struct device_node *np;
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|
const struct div_data *data;
|
|
const struct of_device_id *match;
|
|
void (*setup_function)(struct device_node *, const void *) = function;
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|
|
|
for_each_matching_node(np, clk_match) {
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|
match = of_match_node(clk_match, np);
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|
data = match->data;
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|
setup_function(np, data);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* System clock protection
|
|
*
|
|
* By enabling these critical clocks, we prevent their accidental gating
|
|
* by the framework
|
|
*/
|
|
static void __init sunxi_clock_protect(void)
|
|
{
|
|
struct clk *clk;
|
|
|
|
/* memory bus clock - sun5i+ */
|
|
clk = clk_get(NULL, "mbus");
|
|
if (!IS_ERR(clk)) {
|
|
clk_prepare_enable(clk);
|
|
clk_put(clk);
|
|
}
|
|
|
|
/* DDR clock - sun4i+ */
|
|
clk = clk_get(NULL, "pll5_ddr");
|
|
if (!IS_ERR(clk)) {
|
|
clk_prepare_enable(clk);
|
|
clk_put(clk);
|
|
}
|
|
}
|
|
|
|
static void __init sunxi_init_clocks(void)
|
|
{
|
|
/* Register factor clocks */
|
|
of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
|
|
|
|
/* Register divider clocks */
|
|
of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
|
|
|
|
/* Register divided output clocks */
|
|
of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
|
|
|
|
/* Register mux clocks */
|
|
of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
|
|
|
|
/* Register gate clocks */
|
|
of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
|
|
|
|
/* Enable core system clocks */
|
|
sunxi_clock_protect();
|
|
}
|
|
CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
|
|
CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
|
|
CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks);
|
|
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks);
|
|
CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks);
|