479 строки
13 KiB
C
479 строки
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drmP.h>
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#include "sun8i_vi_layer.h"
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#include "sun8i_mixer.h"
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#include "sun8i_vi_scaler.h"
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static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
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int overlay, bool enable, unsigned int zpos,
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unsigned int old_zpos)
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{
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u32 val, bld_base, ch_base;
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bld_base = sun8i_blender_base(mixer);
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ch_base = sun8i_channel_base(mixer, channel);
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DRM_DEBUG_DRIVER("%sabling VI channel %d overlay %d\n",
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enable ? "En" : "Dis", channel, overlay);
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if (enable)
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val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
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else
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val = 0;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
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if (!enable || zpos != old_zpos) {
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
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SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
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0);
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ROUTE(bld_base),
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SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
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0);
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}
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if (enable) {
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val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
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val, val);
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val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ROUTE(bld_base),
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SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
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val);
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}
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}
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static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane,
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unsigned int zpos)
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{
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struct drm_plane_state *state = plane->state;
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const struct drm_format_info *format = state->fb->format;
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u32 src_w, src_h, dst_w, dst_h;
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u32 bld_base, ch_base;
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u32 outsize, insize;
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u32 hphase, vphase;
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u32 hn = 0, hm = 0;
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u32 vn = 0, vm = 0;
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bool subsampled;
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DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n",
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channel, overlay);
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bld_base = sun8i_blender_base(mixer);
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ch_base = sun8i_channel_base(mixer, channel);
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src_w = drm_rect_width(&state->src) >> 16;
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src_h = drm_rect_height(&state->src) >> 16;
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dst_w = drm_rect_width(&state->dst);
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dst_h = drm_rect_height(&state->dst);
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hphase = state->src.x1 & 0xffff;
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vphase = state->src.y1 & 0xffff;
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/* make coordinates dividable by subsampling factor */
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if (format->hsub > 1) {
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int mask, remainder;
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mask = format->hsub - 1;
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remainder = (state->src.x1 >> 16) & mask;
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src_w = (src_w + remainder) & ~mask;
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hphase += remainder << 16;
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}
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if (format->vsub > 1) {
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int mask, remainder;
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mask = format->vsub - 1;
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remainder = (state->src.y1 >> 16) & mask;
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src_h = (src_h + remainder) & ~mask;
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vphase += remainder << 16;
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}
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insize = SUN8I_MIXER_SIZE(src_w, src_h);
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outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
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/* Set height and width */
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DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
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(state->src.x1 >> 16) & ~(format->hsub - 1),
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(state->src.y1 >> 16) & ~(format->vsub - 1));
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DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch_base, overlay),
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insize);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch_base),
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insize);
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/*
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* Scaler must be enabled for subsampled formats, so it scales
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* chroma to same size as luma.
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*/
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subsampled = format->hsub > 1 || format->vsub > 1;
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if (insize != outsize || subsampled || hphase || vphase) {
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unsigned int scanline, required;
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struct drm_display_mode *mode;
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u32 hscale, vscale, fps;
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u64 ability;
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DRM_DEBUG_DRIVER("HW scaling is enabled\n");
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mode = &plane->state->crtc->state->mode;
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fps = (mode->clock * 1000) / (mode->vtotal * mode->htotal);
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ability = clk_get_rate(mixer->mod_clk);
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/* BSP algorithm assumes 80% efficiency of VI scaler unit */
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ability *= 80;
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do_div(ability, mode->vdisplay * fps * max(src_w, dst_w));
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required = src_h * 100 / dst_h;
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if (ability < required) {
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DRM_DEBUG_DRIVER("Using vertical coarse scaling\n");
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vm = src_h;
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vn = (u32)ability * dst_h / 100;
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src_h = vn;
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}
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/* it seems that every RGB scaler has buffer for 2048 pixels */
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scanline = subsampled ? mixer->cfg->scanline_yuv : 2048;
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if (src_w > scanline) {
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DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n");
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hm = src_w;
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hn = scanline;
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src_w = hn;
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}
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hscale = (src_w << 16) / dst_w;
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vscale = (src_h << 16) / dst_h;
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sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w,
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dst_h, hscale, vscale, hphase, vphase,
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format);
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sun8i_vi_scaler_enable(mixer, channel, true);
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} else {
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DRM_DEBUG_DRIVER("HW scaling is not needed\n");
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sun8i_vi_scaler_enable(mixer, channel, false);
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}
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_HDS_Y(ch_base),
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SUN8I_MIXER_CHAN_VI_DS_N(hn) |
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SUN8I_MIXER_CHAN_VI_DS_M(hm));
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_HDS_UV(ch_base),
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SUN8I_MIXER_CHAN_VI_DS_N(hn) |
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SUN8I_MIXER_CHAN_VI_DS_M(hm));
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_VDS_Y(ch_base),
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SUN8I_MIXER_CHAN_VI_DS_N(vn) |
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SUN8I_MIXER_CHAN_VI_DS_M(vm));
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base),
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SUN8I_MIXER_CHAN_VI_DS_N(vn) |
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SUN8I_MIXER_CHAN_VI_DS_M(vm));
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/* Set base coordinates */
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DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
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state->dst.x1, state->dst.y1);
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DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
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SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
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outsize);
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return 0;
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}
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static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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const struct de2_fmt_info *fmt_info;
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u32 val, ch_base;
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ch_base = sun8i_channel_base(mixer, channel);
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fmt_info = sun8i_mixer_format_info(state->fb->format->format);
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if (!fmt_info) {
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DRM_DEBUG_DRIVER("Invalid format\n");
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return -EINVAL;
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}
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val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
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if (fmt_info->csc != SUN8I_CSC_MODE_OFF) {
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sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc);
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sun8i_csc_enable_ccsc(mixer, channel, true);
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} else {
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sun8i_csc_enable_ccsc(mixer, channel, false);
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}
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if (fmt_info->rgb)
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val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;
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else
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val = 0;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val);
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/* It seems that YUV formats use global alpha setting. */
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if (mixer->cfg->is_de3)
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base,
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overlay),
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SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK,
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SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA(0xff));
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return 0;
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}
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static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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const struct drm_format_info *format = fb->format;
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struct drm_gem_cma_object *gem;
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u32 dx, dy, src_x, src_y;
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dma_addr_t paddr;
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u32 ch_base;
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int i;
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ch_base = sun8i_channel_base(mixer, channel);
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/* Adjust x and y to be dividable by subsampling factor */
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src_x = (state->src.x1 >> 16) & ~(format->hsub - 1);
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src_y = (state->src.y1 >> 16) & ~(format->vsub - 1);
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for (i = 0; i < format->num_planes; i++) {
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/* Get the physical address of the buffer in memory */
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gem = drm_fb_cma_get_gem_obj(fb, i);
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DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
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/* Compute the start of the displayed memory */
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paddr = gem->paddr + fb->offsets[i];
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dx = src_x;
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dy = src_y;
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if (i > 0) {
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dx /= format->hsub;
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dy /= format->vsub;
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}
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/* Fixup framebuffer address for src coordinates */
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paddr += dx * format->cpp[i];
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paddr += dy * fb->pitches[i];
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/* Set the line width */
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DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
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i + 1, fb->pitches[i]);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch_base,
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overlay, i),
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fb->pitches[i]);
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DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
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i + 1, &paddr);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base,
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overlay, i),
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lower_32_bits(paddr));
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}
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return 0;
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}
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static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
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struct drm_crtc *crtc = state->crtc;
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struct drm_crtc_state *crtc_state;
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int min_scale, max_scale;
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if (!crtc)
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return 0;
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crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
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if (WARN_ON(!crtc_state))
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return -EINVAL;
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min_scale = DRM_PLANE_HELPER_NO_SCALING;
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max_scale = DRM_PLANE_HELPER_NO_SCALING;
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if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
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min_scale = SUN8I_VI_SCALER_SCALE_MIN;
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max_scale = SUN8I_VI_SCALER_SCALE_MAX;
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}
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return drm_atomic_helper_check_plane_state(state, crtc_state,
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min_scale, max_scale,
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true, true);
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}
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static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
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unsigned int old_zpos = old_state->normalized_zpos;
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struct sun8i_mixer *mixer = layer->mixer;
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sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
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old_zpos);
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}
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static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
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unsigned int zpos = plane->state->normalized_zpos;
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unsigned int old_zpos = old_state->normalized_zpos;
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struct sun8i_mixer *mixer = layer->mixer;
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if (!plane->state->visible) {
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sun8i_vi_layer_enable(mixer, layer->channel,
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layer->overlay, false, 0, old_zpos);
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return;
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}
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sun8i_vi_layer_update_coord(mixer, layer->channel,
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layer->overlay, plane, zpos);
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sun8i_vi_layer_update_formats(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_vi_layer_update_buffer(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay,
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true, zpos, old_zpos);
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}
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static struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
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.prepare_fb = drm_gem_fb_prepare_fb,
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.atomic_check = sun8i_vi_layer_atomic_check,
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.atomic_disable = sun8i_vi_layer_atomic_disable,
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.atomic_update = sun8i_vi_layer_atomic_update,
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};
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static const struct drm_plane_funcs sun8i_vi_layer_funcs = {
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.destroy = drm_plane_cleanup,
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.disable_plane = drm_atomic_helper_disable_plane,
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.reset = drm_atomic_helper_plane_reset,
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.update_plane = drm_atomic_helper_update_plane,
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};
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/*
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* While all RGB formats are supported, VI planes don't support
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* alpha blending, so there is no point having formats with alpha
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* channel if their opaque analog exist.
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*/
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static const u32 sun8i_vi_layer_formats[] = {
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DRM_FORMAT_ABGR1555,
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DRM_FORMAT_ABGR4444,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_ARGB4444,
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DRM_FORMAT_BGR565,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_BGRA5551,
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DRM_FORMAT_BGRA4444,
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DRM_FORMAT_BGRX8888,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_RGBA4444,
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DRM_FORMAT_RGBA5551,
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DRM_FORMAT_RGBX8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_NV16,
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DRM_FORMAT_NV12,
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DRM_FORMAT_NV21,
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DRM_FORMAT_NV61,
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DRM_FORMAT_UYVY,
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DRM_FORMAT_VYUY,
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DRM_FORMAT_YUYV,
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DRM_FORMAT_YVYU,
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DRM_FORMAT_YUV411,
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DRM_FORMAT_YUV420,
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DRM_FORMAT_YUV422,
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DRM_FORMAT_YUV444,
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DRM_FORMAT_YVU411,
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DRM_FORMAT_YVU420,
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DRM_FORMAT_YVU422,
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DRM_FORMAT_YVU444,
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};
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struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
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struct sun8i_mixer *mixer,
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int index)
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{
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struct sun8i_vi_layer *layer;
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unsigned int plane_cnt;
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int ret;
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layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
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if (!layer)
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return ERR_PTR(-ENOMEM);
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/* possible crtcs are set later */
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ret = drm_universal_plane_init(drm, &layer->plane, 0,
|
|
&sun8i_vi_layer_funcs,
|
|
sun8i_vi_layer_formats,
|
|
ARRAY_SIZE(sun8i_vi_layer_formats),
|
|
NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
|
|
if (ret) {
|
|
dev_err(drm->dev, "Couldn't initialize layer\n");
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
|
|
|
|
ret = drm_plane_create_zpos_property(&layer->plane, index,
|
|
0, plane_cnt - 1);
|
|
if (ret) {
|
|
dev_err(drm->dev, "Couldn't add zpos property\n");
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
|
|
layer->mixer = mixer;
|
|
layer->channel = index;
|
|
layer->overlay = 0;
|
|
|
|
return layer;
|
|
}
|