568 строки
16 KiB
Plaintext
568 строки
16 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for K2G EVM
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*
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* Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
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*/
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/dts-v1/;
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#include "keystone-k2g.dtsi"
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/ {
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compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
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model = "Texas Instruments K2G General Purpose EVM";
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memory@800000000 {
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device_type = "memory";
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reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dsp_common_memory: dsp-common-memory@81f800000 {
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compatible = "shared-dma-pool";
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reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
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reusable;
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status = "okay";
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};
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};
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vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
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compatible = "regulator-fixed";
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regulator-name = "mmc0_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 {
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compatible = "regulator-fixed";
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regulator-name = "ldo1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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vcc1v8_ldo2_reg: fixedregulator-vcc1v8-ldo2 {
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compatible = "regulator-fixed";
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regulator-name = "ldo2";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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hdmi: connector {
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compatible = "hdmi-connector";
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label = "hdmi";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&sii9022_out>;
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};
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};
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};
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aud_mclk: aud_mclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12288000>;
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};
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sound0: sound@0 {
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compatible = "simple-audio-card";
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simple-audio-card,name = "K2G-EVM";
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simple-audio-card,widgets =
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"Headphone", "Headphone Jack",
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"Line", "Line In";
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simple-audio-card,routing =
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"Headphone Jack", "HPLOUT",
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"Headphone Jack", "HPROUT",
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"LINE1L", "Line In",
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"LINE1R", "Line In";
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simple-audio-card,dai-link@0 {
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format = "i2s";
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bitclock-master = <&sound0_0_master>;
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frame-master = <&sound0_0_master>;
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sound0_0_master: cpu {
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sound-dai = <&mcasp2>;
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clocks = <&k2g_clks 0x6 1>;
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system-clock-direction-out;
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};
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codec {
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sound-dai = <&tlv320aic3106>;
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clocks = <&aud_mclk>;
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};
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};
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simple-audio-card,dai-link@1 {
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format = "i2s";
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bitclock-master = <&sound0_1_master>;
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frame-master = <&sound0_1_master>;
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sound0_1_master: cpu {
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sound-dai = <&mcasp2>;
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clocks = <&k2g_clks 0x6 1>;
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system-clock-direction-out;
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};
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codec {
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sound-dai = <&sii9022>;
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clocks = <&aud_mclk>;
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};
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};
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};
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};
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&k2g_pinctrl {
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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>;
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};
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mmc0_pins: pinmux_mmc0_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
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K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */
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K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */
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K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */
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K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */
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K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */
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K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */
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K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */
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K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */
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K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */
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K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
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K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
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K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
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K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
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K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
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K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
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>;
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};
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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>;
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};
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */
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K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */
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>;
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};
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ecap0_pins: ecap0_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */
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>;
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};
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spi1_pins: pinmux_spi1_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */
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K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */
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K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */
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K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */
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>;
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};
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qspi_pins: pinmux_qspi_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
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K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
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K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
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K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
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K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
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K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
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K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
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>;
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};
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uart2_pins: pinmux_uart2_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */
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K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */
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>;
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};
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dcan0_pins: pinmux_dcan0_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */
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K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */
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>;
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};
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dcan1_pins: pinmux_dcan1_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */
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K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */
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>;
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};
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emac_pins: pinmux_emac_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */
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K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */
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K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */
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K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */
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K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */
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K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */
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K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */
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K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */
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K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */
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K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */
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K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */
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K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */
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>;
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};
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mdio_pins: pinmux_mdio_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */
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K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
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>;
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};
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vout_pins: pinmux_vout_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */
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K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */
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K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */
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K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */
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K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */
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K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */
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K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */
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K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */
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K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */
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K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */
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K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */
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K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */
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K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */
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K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */
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K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */
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K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */
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K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */
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K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */
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K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */
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K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */
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K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */
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K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */
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K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */
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K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */
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K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */
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K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */
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K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */
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K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */
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K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */
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>;
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};
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mcasp2_pins: pinmux_mcasp2_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */
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K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */
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K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo10.mcasp2_afsx */
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K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo12.mcasp2_aclkx */
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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vmmc-supply = <&vcc3v3_dcin_reg>;
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vqmmc-supply = <&vcc3v3_dcin_reg>;
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cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
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vqmmc-supply = <&vcc1v8_ldo1_reg>;
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ti,non-removable;
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status = "okay";
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};
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&dsp0 {
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memory-region = <&dsp_common_memory>;
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status = "okay";
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};
|
|
|
|
&i2c0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
status = "okay";
|
|
|
|
eeprom@50 {
|
|
compatible = "atmel,24c1024";
|
|
reg = <0x50>;
|
|
};
|
|
};
|
|
|
|
&keystone_usb0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb0_phy {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb0 {
|
|
dr_mode = "host";
|
|
status = "okay";
|
|
};
|
|
|
|
&keystone_usb1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb1_phy {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb1 {
|
|
dr_mode = "peripheral";
|
|
status = "okay";
|
|
};
|
|
|
|
&ecap0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ecap0_pins>;
|
|
};
|
|
|
|
&spi1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_pins>;
|
|
status = "okay";
|
|
|
|
spi_nor: flash@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "jedec,spi-nor";
|
|
spi-max-frequency = <5000000>;
|
|
m25p,fast-read;
|
|
reg = <0>;
|
|
|
|
partition@0 {
|
|
label = "u-boot-spl";
|
|
reg = <0x0 0x100000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@1 {
|
|
label = "misc";
|
|
reg = <0x100000 0xf00000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qspi_pins>;
|
|
cdns,rclk-en;
|
|
|
|
flash0: m25p80@0 {
|
|
compatible = "s25fl512s", "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>;
|
|
spi-max-frequency = <96000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
cdns,read-delay = <5>;
|
|
cdns,tshsl-ns = <500>;
|
|
cdns,tsd2d-ns = <500>;
|
|
cdns,tchsh-ns = <119>;
|
|
cdns,tslch-ns = <119>;
|
|
|
|
partition@0 {
|
|
label = "QSPI.u-boot-spl-os";
|
|
reg = <0x00000000 0x00100000>;
|
|
};
|
|
partition@1 {
|
|
label = "QSPI.u-boot-env";
|
|
reg = <0x00100000 0x00040000>;
|
|
};
|
|
partition@2 {
|
|
label = "QSPI.skern";
|
|
reg = <0x00140000 0x0040000>;
|
|
};
|
|
partition@3 {
|
|
label = "QSPI.pmmc-firmware";
|
|
reg = <0x00180000 0x0040000>;
|
|
};
|
|
partition@4 {
|
|
label = "QSPI.kernel";
|
|
reg = <0x001C0000 0x0800000>;
|
|
};
|
|
partition@5 {
|
|
label = "QSPI.file-system";
|
|
reg = <0x009C0000 0x3640000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&uart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&dcan0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&dcan0_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&dcan1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&dcan1_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&qmss {
|
|
status = "okay";
|
|
};
|
|
|
|
&knav_dmas {
|
|
status = "okay";
|
|
};
|
|
|
|
&mdio {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mdio_pins>;
|
|
status = "okay";
|
|
ethphy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
&gbe0 {
|
|
phy-handle = <ðphy0>;
|
|
phy-mode = "rgmii-rxid";
|
|
status = "okay";
|
|
};
|
|
|
|
&netcp {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&emac_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_pins>;
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
|
|
sii9022: sii9022@3b {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "sil,sii9022";
|
|
reg = <0x3b>;
|
|
|
|
sil,i2s-data-lanes = < 0 >;
|
|
clocks = <&aud_mclk>;
|
|
clock-names = "mclk";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
sii9022_in: endpoint {
|
|
remote-endpoint = <&dpi_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
sii9022_out: endpoint {
|
|
remote-endpoint = <&hdmi_connector_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tlv320aic3106: tlv320aic3106@1b {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "ti,tlv320aic3106";
|
|
reg = <0x1b>;
|
|
status = "okay";
|
|
|
|
/* Regulators */
|
|
AVDD-supply = <&vcc3v3_dcin_reg>;
|
|
IOVDD-supply = <&vcc3v3_dcin_reg>;
|
|
DRVDD-supply = <&vcc3v3_dcin_reg>;
|
|
DVDD-supply = <&vcc1v8_ldo2_reg>;
|
|
};
|
|
};
|
|
|
|
&dss {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&vout_pins>;
|
|
status = "ok";
|
|
|
|
port {
|
|
dpi_out: endpoint {
|
|
remote-endpoint = <&sii9022_in>;
|
|
data-lines = <24>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&mcasp2 {
|
|
#sound-dai-cells = <0>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcasp2_pins>;
|
|
|
|
assigned-clocks = <&k2g_clks 0x4c 2>, <&k2g_clks 0x6 1>;
|
|
assigned-clock-parents = <0>, <&k2g_clks 0x6 2>;
|
|
assigned-clock-rates = <22579200>, <0>;
|
|
|
|
status = "okay";
|
|
|
|
op-mode = <0>; /* MCASP_IIS_MODE */
|
|
tdm-slots = <2>;
|
|
/* 6 serializer */
|
|
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
|
0 0 1 2 0 0 // AXR2: TX, AXR3: rx
|
|
>;
|
|
tx-num-evt = <32>;
|
|
rx-num-evt = <32>;
|
|
};
|