395 строки
19 KiB
Plaintext
395 строки
19 KiB
Plaintext
====================================================================
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= Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0 =
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= README for =
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= The Linux Operating System =
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====================================================================
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The following information is available in this file:
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1. Supported Hardware
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2. Version History
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3. Command Line Options
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4. Contacting Adaptec
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1. Supported Hardware
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The following Adaptec SCSI Chips and Host Adapters are supported by
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the aic7xxx driver.
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Chip MIPS Host Bus MaxSync MaxWidth SCBs Notes
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---------------------------------------------------------------
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aic7770 10 EISA/VL 10MHz 16Bit 4 1
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aic7850 10 PCI/32 10MHz 8Bit 3
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aic7855 10 PCI/32 10MHz 8Bit 3
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aic7856 10 PCI/32 10MHz 8Bit 3
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aic7859 10 PCI/32 20MHz 8Bit 3
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aic7860 10 PCI/32 20MHz 8Bit 3
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aic7870 10 PCI/32 10MHz 16Bit 16
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aic7880 10 PCI/32 20MHz 16Bit 16
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aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
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aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
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aic7892 20 PCI/64-66 80MHz 16Bit 16 3 4 5 6 7 8
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aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5
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aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8
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aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8
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aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8
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aic7899 20 PCI/64-66 80MHz 16Bit 16 2 3 4 5 6 7 8
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1. Multiplexed Twin Channel Device - One controller servicing two
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busses.
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2. Multi-function Twin Channel Device - Two controllers on one chip.
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3. Command Channel Secondary DMA Engine - Allows scatter gather list
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and SCB prefetch.
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4. 64 Byte SCB Support - Allows disconnected, unttagged request table
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for all possible target/lun combinations.
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5. Block Move Instruction Support - Doubles the speed of certain
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sequencer operations.
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6. `Bayonet' style Scatter Gather Engine - Improves S/G prefetch
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performance.
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7. Queuing Registers - Allows queuing of new transactions without
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pausing the sequencer.
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8. Multiple Target IDs - Allows the controller to respond to selection
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as a target on multiple SCSI IDs.
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Controller Chip Host-Bus Int-Connectors Ext-Connectors Notes
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--------------------------------------------------------------------------
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AHA-274X[A] aic7770 EISA SE-50M SE-HD50F
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AHA-274X[A]W aic7770 EISA SE-HD68F SE-HD68F
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SE-50M
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AHA-274X[A]T aic7770 EISA 2 X SE-50M SE-HD50F
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AHA-2842 aic7770 VL SE-50M SE-HD50F
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AHA-2940AU aic7860 PCI/32 SE-50M SE-HD50F
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AVA-2902I aic7860 PCI/32 SE-50M
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AVA-2902E aic7860 PCI/32 SE-50M
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AVA-2906 aic7856 PCI/32 SE-50M SE-DB25F
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APC-7850 aic7850 PCI/32 SE-50M 1
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AVA-2940 aic7860 PCI/32 SE-50M
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AHA-2920B aic7860 PCI/32 SE-50M
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AHA-2930B aic7860 PCI/32 SE-50M
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AHA-2920C aic7856 PCI/32 SE-50M SE-HD50F
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AHA-2930C aic7860 PCI/32 SE-50M
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AHA-2930C aic7860 PCI/32 SE-50M
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AHA-2910C aic7860 PCI/32 SE-50M
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AHA-2915C aic7860 PCI/32 SE-50M
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AHA-2940AU/CN aic7860 PCI/32 SE-50M SE-HD50F
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AHA-2944W aic7870 PCI/32 HVD-HD68F HVD-HD68F
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HVD-50M
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AHA-3940W aic7870 PCI/32 2 X SE-HD68F SE-HD68F 2
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AHA-2940UW aic7880 PCI/32 SE-HD68F
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SE-50M SE-HD68F
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AHA-2940U aic7880 PCI/32 SE-50M SE-HD50F
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AHA-2940D aic7880 PCI/32
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aHA-2940 A/T aic7880 PCI/32
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AHA-2940D A/T aic7880 PCI/32
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AHA-3940UW aic7880 PCI/32 2 X SE-HD68F SE-HD68F 3
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AHA-3940UWD aic7880 PCI/32 2 X SE-HD68F 2 X SE-VHD68F 3
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AHA-3940U aic7880 PCI/32 2 X SE-50M SE-HD50F 3
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AHA-2944UW aic7880 PCI/32 HVD-HD68F HVD-HD68F
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HVD-50M
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AHA-3944UWD aic7880 PCI/32 2 X HVD-HD68F 2 X HVD-VHD68F 3
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AHA-4944UW aic7880 PCI/32
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AHA-2930UW aic7880 PCI/32
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AHA-2940UW Pro aic7880 PCI/32 SE-HD68F SE-HD68F 4
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SE-50M
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AHA-2940UW/CN aic7880 PCI/32
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AHA-2940UDual aic7895 PCI/32
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AHA-2940UWDual aic7895 PCI/32
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AHA-3940UWD aic7895 PCI/32
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AHA-3940AUW aic7895 PCI/32
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AHA-3940AUWD aic7895 PCI/32
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AHA-3940AU aic7895 PCI/32
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AHA-3944AUWD aic7895 PCI/32 2 X HVD-HD68F 2 X HVD-VHD68F
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AHA-2940U2B aic7890 PCI/32 LVD-HD68F LVD-HD68F
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AHA-2940U2 OEM aic7891 PCI/64
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AHA-2940U2W aic7890 PCI/32 LVD-HD68F LVD-HD68F
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SE-HD68F
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SE-50M
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AHA-2950U2B aic7891 PCI/64 LVD-HD68F LVD-HD68F
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AHA-2930U2 aic7890 PCI/32 LVD-HD68F SE-HD50F
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SE-50M
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AHA-3950U2B aic7897 PCI/64
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AHA-3950U2D aic7897 PCI/64
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AHA-29160 aic7892 PCI/64-66
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AHA-29160 CPQ aic7892 PCI/64-66
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AHA-29160N aic7892 PCI/32 LVD-HD68F SE-HD50F
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SE-50M
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AHA-29160LP aic7892 PCI/64-66
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AHA-19160 aic7892 PCI/64-66
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AHA-29150LP aic7892 PCI/64-66
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AHA-29130LP aic7892 PCI/64-66
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AHA-3960D aic7899 PCI/64-66 2 X LVD-HD68F 2 X LVD-VHD68F
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LVD-50M
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AHA-3960D CPQ aic7899 PCI/64-66 2 X LVD-HD68F 2 X LVD-VHD68F
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LVD-50M
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AHA-39160 aic7899 PCI/64-66 2 X LVD-HD68F 2 X LVD-VHD68F
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LVD-50M
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1. No BIOS support
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2. DEC21050 PCI-PCI bridge with multiple controller chips on secondary bus
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3. DEC2115X PCI-PCI bridge with multiple controller chips on secondary bus
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4. All three SCSI connectors may be used simultaneously without
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SCSI "stub" effects.
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2. Version History
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7.0 (4th August, 2005)
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- Updated driver to use SCSI transport class infrastructure
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- Upported sequencer and core fixes from last adaptec released
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version of the driver.
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6.2.36 (June 3rd, 2003)
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- Correct code that disables PCI parity error checking.
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- Correct and simplify handling of the ignore wide residue
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message. The previous code would fail to report a residual
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if the transaction data length was even and we received
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an IWR message.
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- Add support for the 2.5.X EISA framework.
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- Update for change in 2.5.X SCSI proc FS interface.
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- Correct Domain Validation command-line option parsing.
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- When negotiation async via an 8bit WDTR message, send
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an SDTR with an offset of 0 to be sure the target
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knows we are async. This works around a firmware defect
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in the Quantum Atlas 10K.
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- Clear PCI error state during driver attach so that we
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don't disable memory mapped I/O due to a stray write
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by some other driver probe that occurred before we
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claimed the controller.
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6.2.35 (May 14th, 2003)
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- Fix a few GCC 3.3 compiler warnings.
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- Correct operation on EISA Twin Channel controller.
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- Add support for 2.5.X's scsi_report_device_reset().
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6.2.34 (May 5th, 2003)
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- Fix locking regression instroduced in 6.2.29 that
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could cause a lock order reversal between the io_request_lock
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and our per-softc lock. This was only possible on RH9,
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SuSE, and kernel.org 2.4.X kernels.
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6.2.33 (April 30th, 2003)
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- Dynamically disable PCI parity error reporting after
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10 errors are reported to the user. These errors are
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the result of some other device issuing PCI transactions
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with bad parity. Once the user has been informed of the
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problem, continuing to report the errors just degrades
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our performance.
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6.2.32 (March 28th, 2003)
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- Dynamically sized S/G lists to avoid SCSI malloc
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pool fragmentation and SCSI mid-layer deadlock.
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6.2.28 (January 20th, 2003)
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- Domain Validation Fixes
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- Add ability to disable PCI parity error checking.
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- Enhanced Memory Mapped I/O probe
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6.2.20 (November 7th, 2002)
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- Added Domain Validation.
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3. Command Line Options
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WARNING: ALTERING OR ADDING THESE DRIVER PARAMETERS
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INCORRECTLY CAN RENDER YOUR SYSTEM INOPERABLE.
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USE THEM WITH CAUTION.
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Edit the file "modprobe.conf" in the directory /etc and add/edit a
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line containing 'options aic7xxx aic7xxx=[command[,command...]]' where
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'command' is one or more of the following:
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-----------------------------------------------------------------
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Option: verbose
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Definition: enable additional informative messages during
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driver operation.
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Possible Values: This option is a flag
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Default Value: disabled
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-----------------------------------------------------------------
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Option: debug:[value]
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Definition: Enables various levels of debugging information
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Possible Values: 0x0000 = no debugging, 0xffff = full debugging
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Default Value: 0x0000
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-----------------------------------------------------------------
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Option: no_probe
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Option: probe_eisa_vl
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Definition: Do not probe for EISA/VLB controllers.
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This is a toggle. If the driver is compiled
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to not probe EISA/VLB controllers by default,
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specifying "no_probe" will enable this probing.
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If the driver is compiled to probe EISA/VLB
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controllers by default, specifying "no_probe"
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will disable this probing.
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Possible Values: This option is a toggle
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Default Value: EISA/VLB probing is disabled by default.
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-----------------------------------------------------------------
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Option: pci_parity
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Definition: Toggles the detection of PCI parity errors.
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On many motherboards with VIA chipsets,
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PCI parity is not generated correctly on the
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PCI bus. It is impossible for the hardware to
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differentiate between these "spurious" parity
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errors and real parity errors. The symptom of
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this problem is a stream of the message:
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"scsi0: Data Parity Error Detected during address or write data phase"
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output by the driver.
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Possible Values: This option is a toggle
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Default Value: PCI Parity Error reporting is disabled
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-----------------------------------------------------------------
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Option: no_reset
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Definition: Do not reset the bus during the initial probe
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phase
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Possible Values: This option is a flag
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Default Value: disabled
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-----------------------------------------------------------------
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Option: extended
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Definition: Force extended translation on the controller
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Possible Values: This option is a flag
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Default Value: disabled
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-----------------------------------------------------------------
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Option: periodic_otag
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Definition: Send an ordered tag periodically to prevent
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tag starvation. Needed for some older devices
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Possible Values: This option is a flag
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Default Value: disabled
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-----------------------------------------------------------------
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Option: reverse_scan
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Definition: Probe the scsi bus in reverse order, starting
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with target 15
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Possible Values: This option is a flag
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Default Value: disabled
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-----------------------------------------------------------------
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Option: global_tag_depth:[value]
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Definition: Global tag depth for all targets on all busses.
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This option sets the default tag depth which
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may be selectively overridden vi the tag_info
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option.
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Possible Values: 1 - 253
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Default Value: 32
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-----------------------------------------------------------------
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Option: tag_info:{{value[,value...]}[,{value[,value...]}...]}
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Definition: Set the per-target tagged queue depth on a
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per controller basis. Both controllers and targets
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may be ommitted indicating that they should retain
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the default tag depth.
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Examples: tag_info:{{16,32,32,64,8,8,,32,32,32,32,32,32,32,32,32}
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On Controller 0
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specifies a tag depth of 16 for target 0
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specifies a tag depth of 64 for target 3
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specifies a tag depth of 8 for targets 4 and 5
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leaves target 6 at the default
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specifies a tag depth of 32 for targets 1,2,7-15
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All other targets retain the default depth.
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tag_info:{{},{32,,32}}
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On Controller 1
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specifies a tag depth of 32 for targets 0 and 2
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All other targets retain the default depth.
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Possible Values: 1 - 253
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Default Value: 32
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-----------------------------------------------------------------
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Option: seltime:[value]
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Definition: Specifies the selection timeout value
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Possible Values: 0 = 256ms, 1 = 128ms, 2 = 64ms, 3 = 32ms
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Default Value: 0
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-----------------------------------------------------------------
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Option: dv: {value[,value...]}
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Definition: Set Domain Validation Policy on a per-controller basis.
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Controllers may be ommitted indicating that
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they should retain the default read streaming setting.
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Example: dv:{-1,0,,1,1,0}
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On Controller 0 leave DV at its default setting.
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On Controller 1 disable DV.
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Skip configuration on Controller 2.
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On Controllers 3 and 4 enable DV.
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On Controller 5 disable DV.
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Possible Values: < 0 Use setting from serial EEPROM.
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0 Disable DV
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> 0 Enable DV
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Default Value: SCSI-Select setting on controllers with a SCSI Select
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option for DV. Otherwise, on for controllers supporting
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U160 speeds and off for all other controller types.
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-----------------------------------------------------------------
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Example:
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'options aic7xxx aic7xxx=verbose,no_probe,tag_info:{{},{,,10}},seltime:1'
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enables verbose logging, Disable EISA/VLB probing,
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and set tag depth on Controller 1/Target 2 to 10 tags.
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4. Adaptec Customer Support
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A Technical Support Identification (TSID) Number is required for
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Adaptec technical support.
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- The 12-digit TSID can be found on the white barcode-type label
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included inside the box with your product. The TSID helps us
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provide more efficient service by accurately identifying your
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product and support status.
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Support Options
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- Search the Adaptec Support Knowledgebase (ASK) at
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http://ask.adaptec.com for articles, troubleshooting tips, and
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frequently asked questions about your product.
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- For support via Email, submit your question to Adaptec's
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Technical Support Specialists at http://ask.adaptec.com/.
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North America
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- Visit our Web site at http://www.adaptec.com/.
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- For information about Adaptec's support options, call
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408-957-2550, 24 hours a day, 7 days a week.
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- To speak with a Technical Support Specialist,
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* For hardware products, call 408-934-7274,
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Monday to Friday, 3:00 am to 5:00 pm, PDT.
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* For RAID and Fibre Channel products, call 321-207-2000,
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Monday to Friday, 3:00 am to 5:00 pm, PDT.
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To expedite your service, have your computer with you.
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- To order Adaptec products, including accessories and cables,
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call 408-957-7274. To order cables online go to
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http://www.adaptec.com/buy-cables/.
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Europe
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- Visit our Web site at http://www.adaptec-europe.com/.
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- To speak with a Technical Support Specialist, call, or email,
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* German: +49 89 4366 5522, Monday-Friday, 9:00-17:00 CET,
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http://ask-de.adaptec.com/.
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* French: +49 89 4366 5533, Monday-Friday, 9:00-17:00 CET,
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http://ask-fr.adaptec.com/.
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* English: +49 89 4366 5544, Monday-Friday, 9:00-17:00 GMT,
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http://ask.adaptec.com/.
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- You can order Adaptec cables online at
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http://www.adaptec.com/buy-cables/.
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Japan
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- Visit our web site at http://www.adaptec.co.jp/.
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- To speak with a Technical Support Specialist, call
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+81 3 5308 6120, Monday-Friday, 9:00 a.m. to 12:00 p.m.,
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1:00 p.m. to 6:00 p.m.
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-------------------------------------------------------------------
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/*
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* Copyright (c) 2003 Adaptec Inc. 691 S. Milpitas Blvd., Milpitas CA 95035 USA.
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* All rights reserved.
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*
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* You are permitted to redistribute, use and modify this README file in whole
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* or in part in conjunction with redistribution of software governed by the
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* General Public License, provided that the following conditions are met:
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* 1. Redistributions of README file must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* 3. Modifications or new contributions must be attributed in a copyright
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* notice identifying the author ("Contributor") and added below the
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* original copyright notice. The copyright notice is for purposes of
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* identifying contributors and should not be deemed as permission to alter
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* the permissions given by Adaptec.
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*
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* THIS README FILE IS PROVIDED BY ADAPTEC AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ANY
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* WARRANTIES OF NON-INFRINGEMENT OR THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* ADAPTEC OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS README
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* FILE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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