187 строки
6.4 KiB
C
187 строки
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* i2sbus driver -- interface register definitions
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*
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* Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
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*/
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#ifndef __I2SBUS_INTERFACE_H
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#define __I2SBUS_INTERFACE_H
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/* i2s bus control registers, at least what we know about them */
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#define __PAD(m,n) u8 __pad##m[n]
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#define _PAD(line, n) __PAD(line, n)
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#define PAD(n) _PAD(__LINE__, (n))
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struct i2s_interface_regs {
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__le32 intr_ctl; /* 0x00 */
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PAD(12);
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__le32 serial_format; /* 0x10 */
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PAD(12);
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__le32 codec_msg_out; /* 0x20 */
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PAD(12);
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__le32 codec_msg_in; /* 0x30 */
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PAD(12);
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__le32 frame_count; /* 0x40 */
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PAD(12);
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__le32 frame_match; /* 0x50 */
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PAD(12);
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__le32 data_word_sizes; /* 0x60 */
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PAD(12);
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__le32 peak_level_sel; /* 0x70 */
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PAD(12);
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__le32 peak_level_in0; /* 0x80 */
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PAD(12);
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__le32 peak_level_in1; /* 0x90 */
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PAD(12);
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/* total size: 0x100 bytes */
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} __attribute__((__packed__));
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/* interrupt register is just a bitfield with
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* interrupt enable and pending bits */
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#define I2S_REG_INTR_CTL 0x00
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# define I2S_INT_FRAME_COUNT (1<<31)
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# define I2S_PENDING_FRAME_COUNT (1<<30)
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# define I2S_INT_MESSAGE_FLAG (1<<29)
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# define I2S_PENDING_MESSAGE_FLAG (1<<28)
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# define I2S_INT_NEW_PEAK (1<<27)
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# define I2S_PENDING_NEW_PEAK (1<<26)
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# define I2S_INT_CLOCKS_STOPPED (1<<25)
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# define I2S_PENDING_CLOCKS_STOPPED (1<<24)
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# define I2S_INT_EXTERNAL_SYNC_ERROR (1<<23)
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# define I2S_PENDING_EXTERNAL_SYNC_ERROR (1<<22)
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# define I2S_INT_EXTERNAL_SYNC_OK (1<<21)
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# define I2S_PENDING_EXTERNAL_SYNC_OK (1<<20)
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# define I2S_INT_NEW_SAMPLE_RATE (1<<19)
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# define I2S_PENDING_NEW_SAMPLE_RATE (1<<18)
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# define I2S_INT_STATUS_FLAG (1<<17)
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# define I2S_PENDING_STATUS_FLAG (1<<16)
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/* serial format register is more interesting :)
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* It contains:
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* - clock source
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* - MClk divisor
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* - SClk divisor
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* - SClk master flag
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* - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
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* - external sample frequency interrupt (don't understand)
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* - external sample frequency
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*/
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#define I2S_REG_SERIAL_FORMAT 0x10
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/* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
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# define I2S_SF_CLOCK_SOURCE_SHIFT 30
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# define I2S_SF_CLOCK_SOURCE_MASK (3<<I2S_SF_CLOCK_SOURCE_SHIFT)
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# define I2S_SF_CLOCK_SOURCE_18MHz (0<<I2S_SF_CLOCK_SOURCE_SHIFT)
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# define I2S_SF_CLOCK_SOURCE_45MHz (1<<I2S_SF_CLOCK_SOURCE_SHIFT)
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# define I2S_SF_CLOCK_SOURCE_49MHz (2<<I2S_SF_CLOCK_SOURCE_SHIFT)
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/* also, let's define the exact clock speeds here, in Hz */
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#define I2S_CLOCK_SPEED_18MHz 18432000
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#define I2S_CLOCK_SPEED_45MHz 45158400
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#define I2S_CLOCK_SPEED_49MHz 49152000
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/* MClk is the clock that drives the codec, usually called its 'system clock'.
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* It is derived by taking only every 'divisor' tick of the clock.
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*/
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# define I2S_SF_MCLKDIV_SHIFT 24
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# define I2S_SF_MCLKDIV_MASK (0x1F<<I2S_SF_MCLKDIV_SHIFT)
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# define I2S_SF_MCLKDIV_1 (0x14<<I2S_SF_MCLKDIV_SHIFT)
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# define I2S_SF_MCLKDIV_3 (0x13<<I2S_SF_MCLKDIV_SHIFT)
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# define I2S_SF_MCLKDIV_5 (0x12<<I2S_SF_MCLKDIV_SHIFT)
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# define I2S_SF_MCLKDIV_14 (0x0E<<I2S_SF_MCLKDIV_SHIFT)
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# define I2S_SF_MCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK)
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static inline int i2s_sf_mclkdiv(int div, int *out)
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{
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int d;
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switch(div) {
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case 1: *out |= I2S_SF_MCLKDIV_1; return 0;
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case 3: *out |= I2S_SF_MCLKDIV_3; return 0;
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case 5: *out |= I2S_SF_MCLKDIV_5; return 0;
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case 14: *out |= I2S_SF_MCLKDIV_14; return 0;
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default:
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if (div%2) return -1;
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d = div/2-1;
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if (d == 0x14 || d == 0x13 || d == 0x12 || d == 0x0E)
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return -1;
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*out |= I2S_SF_MCLKDIV_OTHER(div);
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return 0;
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}
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}
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/* SClk is the clock that drives the i2s wire bus. Note that it is
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* derived from the MClk above by taking only every 'divisor' tick
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* of MClk.
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*/
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# define I2S_SF_SCLKDIV_SHIFT 20
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# define I2S_SF_SCLKDIV_MASK (0xF<<I2S_SF_SCLKDIV_SHIFT)
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# define I2S_SF_SCLKDIV_1 (8<<I2S_SF_SCLKDIV_SHIFT)
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# define I2S_SF_SCLKDIV_3 (9<<I2S_SF_SCLKDIV_SHIFT)
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# define I2S_SF_SCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK)
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static inline int i2s_sf_sclkdiv(int div, int *out)
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{
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int d;
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switch(div) {
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case 1: *out |= I2S_SF_SCLKDIV_1; return 0;
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case 3: *out |= I2S_SF_SCLKDIV_3; return 0;
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default:
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if (div%2) return -1;
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d = div/2-1;
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if (d == 8 || d == 9) return -1;
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*out |= I2S_SF_SCLKDIV_OTHER(div);
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return 0;
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}
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}
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# define I2S_SF_SCLK_MASTER (1<<19)
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/* serial format is the way the data is put to the i2s wire bus */
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# define I2S_SF_SERIAL_FORMAT_SHIFT 16
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# define I2S_SF_SERIAL_FORMAT_MASK (7<<I2S_SF_SERIAL_FORMAT_SHIFT)
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# define I2S_SF_SERIAL_FORMAT_SONY (0<<I2S_SF_SERIAL_FORMAT_SHIFT)
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# define I2S_SF_SERIAL_FORMAT_I2S_64X (1<<I2S_SF_SERIAL_FORMAT_SHIFT)
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# define I2S_SF_SERIAL_FORMAT_I2S_32X (2<<I2S_SF_SERIAL_FORMAT_SHIFT)
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# define I2S_SF_SERIAL_FORMAT_I2S_DAV (4<<I2S_SF_SERIAL_FORMAT_SHIFT)
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# define I2S_SF_SERIAL_FORMAT_I2S_SILABS (5<<I2S_SF_SERIAL_FORMAT_SHIFT)
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/* unknown */
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# define I2S_SF_EXT_SAMPLE_FREQ_INT_SHIFT 12
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# define I2S_SF_EXT_SAMPLE_FREQ_INT_MASK (0xF<<I2S_SF_SAMPLE_FREQ_INT_SHIFT)
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/* probably gives external frequency? */
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# define I2S_SF_EXT_SAMPLE_FREQ_MASK 0xFFF
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/* used to send codec messages, but how isn't clear */
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#define I2S_REG_CODEC_MSG_OUT 0x20
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/* used to receive codec messages, but how isn't clear */
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#define I2S_REG_CODEC_MSG_IN 0x30
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/* frame count reg isn't clear to me yet, but probably useful */
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#define I2S_REG_FRAME_COUNT 0x40
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/* program to some value, and get interrupt if frame count reaches it */
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#define I2S_REG_FRAME_MATCH 0x50
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/* this register describes how the bus transfers data */
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#define I2S_REG_DATA_WORD_SIZES 0x60
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/* number of interleaved input channels */
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# define I2S_DWS_NUM_CHANNELS_IN_SHIFT 24
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# define I2S_DWS_NUM_CHANNELS_IN_MASK (0x1F<<I2S_DWS_NUM_CHANNELS_IN_SHIFT)
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/* word size of input data */
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# define I2S_DWS_DATA_IN_SIZE_SHIFT 16
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# define I2S_DWS_DATA_IN_16BIT (0<<I2S_DWS_DATA_IN_SIZE_SHIFT)
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# define I2S_DWS_DATA_IN_24BIT (3<<I2S_DWS_DATA_IN_SIZE_SHIFT)
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/* number of interleaved output channels */
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# define I2S_DWS_NUM_CHANNELS_OUT_SHIFT 8
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# define I2S_DWS_NUM_CHANNELS_OUT_MASK (0x1F<<I2S_DWS_NUM_CHANNELS_OUT_SHIFT)
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/* word size of output data */
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# define I2S_DWS_DATA_OUT_SIZE_SHIFT 0
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# define I2S_DWS_DATA_OUT_16BIT (0<<I2S_DWS_DATA_OUT_SIZE_SHIFT)
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# define I2S_DWS_DATA_OUT_24BIT (3<<I2S_DWS_DATA_OUT_SIZE_SHIFT)
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/* unknown */
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#define I2S_REG_PEAK_LEVEL_SEL 0x70
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/* unknown */
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#define I2S_REG_PEAK_LEVEL_IN0 0x80
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/* unknown */
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#define I2S_REG_PEAK_LEVEL_IN1 0x90
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#endif /* __I2SBUS_INTERFACE_H */
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