232 строки
5.0 KiB
C
232 строки
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Precise Delay Loops for i386
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*
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* Copyright (C) 1993 Linus Torvalds
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* Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
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* Copyright (C) 2008 Jiri Hladky <hladky _dot_ jiri _at_ gmail _dot_ com>
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*
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* The __delay function must _NOT_ be inlined as its execution time
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* depends wildly on alignment on many x86 processors. The additional
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* jump magic is needed to get the timing stable on all the CPU's
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* we have to worry about.
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*/
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <linux/timex.h>
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#include <linux/preempt.h>
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#include <linux/delay.h>
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#include <asm/processor.h>
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#include <asm/delay.h>
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#include <asm/timer.h>
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#include <asm/mwait.h>
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#ifdef CONFIG_SMP
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# include <asm/smp.h>
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#endif
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static void delay_loop(u64 __loops);
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/*
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* Calibration and selection of the delay mechanism happens only once
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* during boot.
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*/
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static void (*delay_fn)(u64) __ro_after_init = delay_loop;
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static void (*delay_halt_fn)(u64 start, u64 cycles) __ro_after_init;
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/* simple loop based delay: */
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static void delay_loop(u64 __loops)
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{
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unsigned long loops = (unsigned long)__loops;
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asm volatile(
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" test %0,%0 \n"
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" jz 3f \n"
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" jmp 1f \n"
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".align 16 \n"
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"1: jmp 2f \n"
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".align 16 \n"
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"2: dec %0 \n"
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" jnz 2b \n"
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"3: dec %0 \n"
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: "+a" (loops)
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:
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);
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}
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/* TSC based delay: */
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static void delay_tsc(u64 cycles)
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{
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u64 bclock, now;
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int cpu;
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preempt_disable();
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cpu = smp_processor_id();
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bclock = rdtsc_ordered();
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for (;;) {
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now = rdtsc_ordered();
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if ((now - bclock) >= cycles)
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break;
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/* Allow RT tasks to run */
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preempt_enable();
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rep_nop();
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preempt_disable();
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/*
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* It is possible that we moved to another CPU, and
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* since TSC's are per-cpu we need to calculate
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* that. The delay must guarantee that we wait "at
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* least" the amount of time. Being moved to another
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* CPU could make the wait longer but we just need to
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* make sure we waited long enough. Rebalance the
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* counter for this CPU.
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*/
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if (unlikely(cpu != smp_processor_id())) {
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cycles -= (now - bclock);
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cpu = smp_processor_id();
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bclock = rdtsc_ordered();
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}
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}
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preempt_enable();
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}
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/*
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* On Intel the TPAUSE instruction waits until any of:
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* 1) the TSC counter exceeds the value provided in EDX:EAX
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* 2) global timeout in IA32_UMWAIT_CONTROL is exceeded
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* 3) an external interrupt occurs
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*/
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static void delay_halt_tpause(u64 start, u64 cycles)
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{
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u64 until = start + cycles;
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u32 eax, edx;
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eax = lower_32_bits(until);
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edx = upper_32_bits(until);
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/*
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* Hard code the deeper (C0.2) sleep state because exit latency is
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* small compared to the "microseconds" that usleep() will delay.
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*/
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__tpause(TPAUSE_C02_STATE, edx, eax);
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}
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/*
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* On some AMD platforms, MWAITX has a configurable 32-bit timer, that
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* counts with TSC frequency. The input value is the number of TSC cycles
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* to wait. MWAITX will also exit when the timer expires.
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*/
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static void delay_halt_mwaitx(u64 unused, u64 cycles)
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{
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u64 delay;
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delay = min_t(u64, MWAITX_MAX_WAIT_CYCLES, cycles);
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/*
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* Use cpu_tss_rw as a cacheline-aligned, seldomly accessed per-cpu
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* variable as the monitor target.
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*/
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__monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0);
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/*
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* AMD, like Intel, supports the EAX hint and EAX=0xf means, do not
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* enter any deep C-state and we use it here in delay() to minimize
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* wakeup latency.
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*/
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__mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
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}
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/*
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* Call a vendor specific function to delay for a given amount of time. Because
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* these functions may return earlier than requested, check for actual elapsed
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* time and call again until done.
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*/
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static void delay_halt(u64 __cycles)
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{
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u64 start, end, cycles = __cycles;
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/*
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* Timer value of 0 causes MWAITX to wait indefinitely, unless there
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* is a store on the memory monitored by MONITORX.
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*/
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if (!cycles)
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return;
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start = rdtsc_ordered();
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for (;;) {
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delay_halt_fn(start, cycles);
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end = rdtsc_ordered();
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if (cycles <= end - start)
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break;
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cycles -= end - start;
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start = end;
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}
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}
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void __init use_tsc_delay(void)
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{
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if (delay_fn == delay_loop)
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delay_fn = delay_tsc;
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}
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void __init use_tpause_delay(void)
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{
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delay_halt_fn = delay_halt_tpause;
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delay_fn = delay_halt;
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}
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void use_mwaitx_delay(void)
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{
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delay_halt_fn = delay_halt_mwaitx;
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delay_fn = delay_halt;
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}
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int read_current_timer(unsigned long *timer_val)
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{
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if (delay_fn == delay_tsc) {
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*timer_val = rdtsc();
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return 0;
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}
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return -1;
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}
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void __delay(unsigned long loops)
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{
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delay_fn(loops);
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}
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EXPORT_SYMBOL(__delay);
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noinline void __const_udelay(unsigned long xloops)
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{
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unsigned long lpj = this_cpu_read(cpu_info.loops_per_jiffy) ? : loops_per_jiffy;
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int d0;
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xloops *= 4;
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asm("mull %%edx"
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:"=d" (xloops), "=&a" (d0)
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:"1" (xloops), "0" (lpj * (HZ / 4)));
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__delay(++xloops);
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}
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EXPORT_SYMBOL(__const_udelay);
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void __udelay(unsigned long usecs)
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{
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__const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
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}
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EXPORT_SYMBOL(__udelay);
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void __ndelay(unsigned long nsecs)
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{
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__const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
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}
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EXPORT_SYMBOL(__ndelay);
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