236 строки
6.0 KiB
C
236 строки
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#include "phy-mtk-mipi-dsi.h"
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inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_mipi_tx, pll_hw);
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}
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void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
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u32 bits)
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{
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u32 temp = readl(mipi_tx->regs + offset);
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writel(temp & ~bits, mipi_tx->regs + offset);
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}
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void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
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u32 bits)
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{
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u32 temp = readl(mipi_tx->regs + offset);
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writel(temp | bits, mipi_tx->regs + offset);
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}
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void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
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u32 mask, u32 data)
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{
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u32 temp = readl(mipi_tx->regs + offset);
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writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
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}
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int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
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dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
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mipi_tx->data_rate = rate;
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return 0;
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}
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unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
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return mipi_tx->data_rate;
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}
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static int mtk_mipi_tx_power_on(struct phy *phy)
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{
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struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
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int ret;
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/* Power up core and enable PLL */
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ret = clk_prepare_enable(mipi_tx->pll);
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if (ret < 0)
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return ret;
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/* Enable DSI Lane LDO outputs, disable pad tie low */
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mipi_tx->driver_data->mipi_tx_enable_signal(phy);
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return 0;
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}
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static int mtk_mipi_tx_power_off(struct phy *phy)
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{
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struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
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/* Enable pad tie low, disable DSI Lane LDO outputs */
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mipi_tx->driver_data->mipi_tx_disable_signal(phy);
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/* Disable PLL and power down core */
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clk_disable_unprepare(mipi_tx->pll);
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return 0;
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}
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static const struct phy_ops mtk_mipi_tx_ops = {
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.power_on = mtk_mipi_tx_power_on,
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.power_off = mtk_mipi_tx_power_off,
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.owner = THIS_MODULE,
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};
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static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx)
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{
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struct nvmem_cell *cell;
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size_t len;
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u32 *buf;
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cell = nvmem_cell_get(mipi_tx->dev, "calibration-data");
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if (IS_ERR(cell)) {
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dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n");
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return;
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}
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buf = (u32 *)nvmem_cell_read(cell, &len);
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nvmem_cell_put(cell);
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if (IS_ERR(buf)) {
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dev_info(mipi_tx->dev, "can't get data, ignore it\n");
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return;
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}
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if (len < 3 * sizeof(u32)) {
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dev_info(mipi_tx->dev, "invalid calibration data\n");
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kfree(buf);
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return;
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}
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mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) |
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(buf[0] >> 11 & 0x1f);
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mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) |
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(buf[0] >> 1 & 0x1f);
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mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) |
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(buf[1] >> 22 & 0x1f);
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mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) |
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(buf[1] >> 12 & 0x1f);
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mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) |
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(buf[1] >> 2 & 0x1f);
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kfree(buf);
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}
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static int mtk_mipi_tx_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_mipi_tx *mipi_tx;
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const char *ref_clk_name;
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struct clk *ref_clk;
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struct clk_init_data clk_init = {
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.num_parents = 1,
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.parent_names = (const char * const *)&ref_clk_name,
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.flags = CLK_SET_RATE_GATE,
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};
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struct phy *phy;
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struct phy_provider *phy_provider;
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int ret;
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mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
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if (!mipi_tx)
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return -ENOMEM;
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mipi_tx->driver_data = of_device_get_match_data(dev);
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if (!mipi_tx->driver_data)
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return -ENODEV;
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mipi_tx->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mipi_tx->regs))
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return PTR_ERR(mipi_tx->regs);
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ref_clk = devm_clk_get(dev, NULL);
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if (IS_ERR(ref_clk))
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return dev_err_probe(dev, PTR_ERR(ref_clk),
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"Failed to get reference clock\n");
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ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
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&mipi_tx->mipitx_drive);
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/* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
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if (ret < 0)
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mipi_tx->mipitx_drive = 4600;
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/* check the mipitx_drive valid */
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if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) {
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dev_warn(dev, "drive-strength-microamp is invalid %d, not in 3000 ~ 6000\n",
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mipi_tx->mipitx_drive);
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mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
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6000);
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}
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ref_clk_name = __clk_get_name(ref_clk);
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ret = of_property_read_string(dev->of_node, "clock-output-names",
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&clk_init.name);
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if (ret < 0)
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return dev_err_probe(dev, ret, "Failed to read clock-output-names\n");
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clk_init.ops = mipi_tx->driver_data->mipi_tx_clk_ops;
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mipi_tx->pll_hw.init = &clk_init;
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mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
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if (IS_ERR(mipi_tx->pll))
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return dev_err_probe(dev, PTR_ERR(mipi_tx->pll), "Failed to register PLL\n");
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phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
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if (IS_ERR(phy))
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return dev_err_probe(dev, PTR_ERR(phy), "Failed to create MIPI D-PHY\n");
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phy_set_drvdata(phy, mipi_tx);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(phy_provider))
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return PTR_ERR(phy_provider);
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mipi_tx->dev = dev;
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mtk_mipi_tx_get_calibration_datal(mipi_tx);
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return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
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mipi_tx->pll);
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}
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static int mtk_mipi_tx_remove(struct platform_device *pdev)
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{
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of_clk_del_provider(pdev->dev.of_node);
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return 0;
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}
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static const struct of_device_id mtk_mipi_tx_match[] = {
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{ .compatible = "mediatek,mt2701-mipi-tx",
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.data = &mt2701_mipitx_data },
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{ .compatible = "mediatek,mt8173-mipi-tx",
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.data = &mt8173_mipitx_data },
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{ .compatible = "mediatek,mt8183-mipi-tx",
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.data = &mt8183_mipitx_data },
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{ },
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};
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MODULE_DEVICE_TABLE(of, mtk_mipi_tx_match);
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static struct platform_driver mtk_mipi_tx_driver = {
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.probe = mtk_mipi_tx_probe,
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.remove = mtk_mipi_tx_remove,
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.driver = {
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.name = "mediatek-mipi-tx",
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.of_match_table = mtk_mipi_tx_match,
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},
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};
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module_platform_driver(mtk_mipi_tx_driver);
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MODULE_DESCRIPTION("MediaTek MIPI TX Driver");
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MODULE_LICENSE("GPL v2");
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