Jonathan Cameron 721992163e cxl/regs: Fix size of CXL Capability Header Register ... [ Upstream commit 74b0fe8040 ] In CXL 2.0, 8.2.5.1 CXL Capability Header Register: this register is given as 32 bits. 8.2.3 which covers the CXL 2.0 Component registers, including the CXL Capability Header Register states that access restrictions specified in Section 8.2.2 apply. 8.2.2 includes: * A 32 bit register shall be accessed as a 4 Byte quantity. ... If these rules are not followed, the behavior is undefined. Discovered during review of CXL QEMU emulation. Alex Bennée pointed out there was a comment saying that 4 byte registers must be read with a 4 byte read, but 8 byte reads were being emulated. https://lore.kernel.org/qemu-devel/87bkzyd3c7.fsf@linaro.org/ Fixing that, led to this code failing. Whilst a given hardware implementation 'might' work with an 8 byte read, it should not be relied upon. The QEMU emulation v5 will return 0 and log the wrong access width. The code moved, so one fixes tag for where this will directly apply and also a reference to the earlier introduction of the code for backports. Fixes: 0f06157e01 ("cxl/core: Move register mapping infrastructure") Fixes: 08422378c4 ("cxl/pci: Add HDM decoder capabilities") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Ben Widawsky <ben.widawsky@intel.com> Link: https://lore.kernel.org/r/20220201153437.2873-1-Jonathan.Cameron@huawei.com Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-04-08 14:23:30 +02:00
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Makefile	cxl/core: Move memdev management to core	2021-08-06 08:22:54 -07:00
bus.c	cxl for v5.15	2021-09-09 11:48:27 -07:00
core.h	cxl/core: Move memdev management to core	2021-08-06 08:22:54 -07:00
memdev.c	cxl/core: Move memdev management to core	2021-08-06 08:22:54 -07:00
pmem.c	cxl/pmem: Fix Documentation warning	2021-09-07 11:39:01 -07:00
regs.c	cxl/regs: Fix size of CXL Capability Header Register	2022-04-08 14:23:30 +02:00