663 строки
12 KiB
C
663 строки
12 KiB
C
/*
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* arch/powerpc/sysdev/qe_lib/ucc.c
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*
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* QE UCC API Set - UCC specific routines implementations.
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*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/stddef.h>
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#include <linux/spinlock.h>
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#include <linux/export.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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#include <soc/fsl/qe/ucc.h>
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#define UCC_TDM_NUM 8
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#define RX_SYNC_SHIFT_BASE 30
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#define TX_SYNC_SHIFT_BASE 14
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#define RX_CLK_SHIFT_BASE 28
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#define TX_CLK_SHIFT_BASE 12
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int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
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{
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unsigned long flags;
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if (ucc_num > UCC_MAX_NUM - 1)
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return -EINVAL;
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spin_lock_irqsave(&cmxgcr_lock, flags);
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clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
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ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
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spin_unlock_irqrestore(&cmxgcr_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng);
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/* Configure the UCC to either Slow or Fast.
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*
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* A given UCC can be figured to support either "slow" devices (e.g. UART)
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* or "fast" devices (e.g. Ethernet).
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*
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* 'ucc_num' is the UCC number, from 0 - 7.
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*
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* This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit
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* must always be set to 1.
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*/
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int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
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{
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u8 __iomem *guemr;
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/* The GUEMR register is at the same location for both slow and fast
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devices, so we just use uccX.slow.guemr. */
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switch (ucc_num) {
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case 0: guemr = &qe_immr->ucc1.slow.guemr;
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break;
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case 1: guemr = &qe_immr->ucc2.slow.guemr;
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break;
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case 2: guemr = &qe_immr->ucc3.slow.guemr;
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break;
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case 3: guemr = &qe_immr->ucc4.slow.guemr;
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break;
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case 4: guemr = &qe_immr->ucc5.slow.guemr;
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break;
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case 5: guemr = &qe_immr->ucc6.slow.guemr;
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break;
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case 6: guemr = &qe_immr->ucc7.slow.guemr;
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break;
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case 7: guemr = &qe_immr->ucc8.slow.guemr;
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break;
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default:
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return -EINVAL;
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}
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clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
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UCC_GUEMR_SET_RESERVED3 | speed);
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return 0;
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}
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static void get_cmxucr_reg(unsigned int ucc_num, __be32 __iomem **cmxucr,
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unsigned int *reg_num, unsigned int *shift)
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{
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unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3);
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*reg_num = cmx + 1;
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*cmxucr = &qe_immr->qmx.cmxucr[cmx];
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*shift = 16 - 8 * (ucc_num & 2);
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}
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int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
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{
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__be32 __iomem *cmxucr;
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unsigned int reg_num;
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unsigned int shift;
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/* check if the UCC number is in range. */
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if (ucc_num > UCC_MAX_NUM - 1)
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return -EINVAL;
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get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
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if (set)
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setbits32(cmxucr, mask << shift);
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else
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clrbits32(cmxucr, mask << shift);
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return 0;
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}
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int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
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enum comm_dir mode)
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{
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__be32 __iomem *cmxucr;
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unsigned int reg_num;
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unsigned int shift;
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u32 clock_bits = 0;
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/* check if the UCC number is in range. */
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if (ucc_num > UCC_MAX_NUM - 1)
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return -EINVAL;
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/* The communications direction must be RX or TX */
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if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))
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return -EINVAL;
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get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
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switch (reg_num) {
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case 1:
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switch (clock) {
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case QE_BRG1: clock_bits = 1; break;
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case QE_BRG2: clock_bits = 2; break;
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case QE_BRG7: clock_bits = 3; break;
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case QE_BRG8: clock_bits = 4; break;
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case QE_CLK9: clock_bits = 5; break;
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case QE_CLK10: clock_bits = 6; break;
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case QE_CLK11: clock_bits = 7; break;
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case QE_CLK12: clock_bits = 8; break;
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case QE_CLK15: clock_bits = 9; break;
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case QE_CLK16: clock_bits = 10; break;
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default: break;
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}
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break;
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case 2:
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switch (clock) {
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case QE_BRG5: clock_bits = 1; break;
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case QE_BRG6: clock_bits = 2; break;
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case QE_BRG7: clock_bits = 3; break;
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case QE_BRG8: clock_bits = 4; break;
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case QE_CLK13: clock_bits = 5; break;
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case QE_CLK14: clock_bits = 6; break;
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case QE_CLK19: clock_bits = 7; break;
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case QE_CLK20: clock_bits = 8; break;
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case QE_CLK15: clock_bits = 9; break;
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case QE_CLK16: clock_bits = 10; break;
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default: break;
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}
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break;
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case 3:
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switch (clock) {
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case QE_BRG9: clock_bits = 1; break;
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case QE_BRG10: clock_bits = 2; break;
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case QE_BRG15: clock_bits = 3; break;
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case QE_BRG16: clock_bits = 4; break;
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case QE_CLK3: clock_bits = 5; break;
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case QE_CLK4: clock_bits = 6; break;
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case QE_CLK17: clock_bits = 7; break;
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case QE_CLK18: clock_bits = 8; break;
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case QE_CLK7: clock_bits = 9; break;
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case QE_CLK8: clock_bits = 10; break;
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case QE_CLK16: clock_bits = 11; break;
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default: break;
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}
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break;
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case 4:
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switch (clock) {
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case QE_BRG13: clock_bits = 1; break;
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case QE_BRG14: clock_bits = 2; break;
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case QE_BRG15: clock_bits = 3; break;
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case QE_BRG16: clock_bits = 4; break;
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case QE_CLK5: clock_bits = 5; break;
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case QE_CLK6: clock_bits = 6; break;
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case QE_CLK21: clock_bits = 7; break;
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case QE_CLK22: clock_bits = 8; break;
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case QE_CLK7: clock_bits = 9; break;
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case QE_CLK8: clock_bits = 10; break;
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case QE_CLK16: clock_bits = 11; break;
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default: break;
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}
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break;
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default: break;
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}
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/* Check for invalid combination of clock and UCC number */
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if (!clock_bits)
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return -ENOENT;
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if (mode == COMM_DIR_RX)
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shift += 4;
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clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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clock_bits << shift);
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return 0;
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}
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static int ucc_get_tdm_common_clk(u32 tdm_num, enum qe_clock clock)
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{
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int clock_bits = -EINVAL;
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/*
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* for TDM[0, 1, 2, 3], TX and RX use common
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* clock source BRG3,4 and CLK1,2
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* for TDM[4, 5, 6, 7], TX and RX use common
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* clock source BRG12,13 and CLK23,24
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*/
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switch (tdm_num) {
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case 0:
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case 1:
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case 2:
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case 3:
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switch (clock) {
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case QE_BRG3:
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clock_bits = 1;
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break;
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case QE_BRG4:
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clock_bits = 2;
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break;
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case QE_CLK1:
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clock_bits = 4;
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break;
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case QE_CLK2:
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clock_bits = 5;
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break;
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default:
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break;
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}
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break;
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case 4:
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case 5:
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case 6:
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case 7:
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switch (clock) {
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case QE_BRG12:
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clock_bits = 1;
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break;
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case QE_BRG13:
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clock_bits = 2;
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break;
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case QE_CLK23:
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clock_bits = 4;
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break;
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case QE_CLK24:
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clock_bits = 5;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return clock_bits;
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}
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static int ucc_get_tdm_rx_clk(u32 tdm_num, enum qe_clock clock)
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{
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int clock_bits = -EINVAL;
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switch (tdm_num) {
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case 0:
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switch (clock) {
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case QE_CLK3:
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clock_bits = 6;
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break;
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case QE_CLK8:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 1:
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switch (clock) {
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case QE_CLK5:
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clock_bits = 6;
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break;
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case QE_CLK10:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 2:
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switch (clock) {
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case QE_CLK7:
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clock_bits = 6;
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break;
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case QE_CLK12:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 3:
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switch (clock) {
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case QE_CLK9:
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clock_bits = 6;
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break;
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case QE_CLK14:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 4:
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switch (clock) {
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case QE_CLK11:
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clock_bits = 6;
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break;
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case QE_CLK16:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 5:
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switch (clock) {
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case QE_CLK13:
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clock_bits = 6;
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break;
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case QE_CLK18:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 6:
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switch (clock) {
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case QE_CLK15:
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clock_bits = 6;
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break;
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case QE_CLK20:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 7:
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switch (clock) {
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case QE_CLK17:
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clock_bits = 6;
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break;
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case QE_CLK22:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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}
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return clock_bits;
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}
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static int ucc_get_tdm_tx_clk(u32 tdm_num, enum qe_clock clock)
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{
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int clock_bits = -EINVAL;
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switch (tdm_num) {
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case 0:
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switch (clock) {
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case QE_CLK4:
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clock_bits = 6;
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break;
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case QE_CLK9:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 1:
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switch (clock) {
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case QE_CLK6:
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clock_bits = 6;
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break;
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case QE_CLK11:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 2:
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switch (clock) {
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case QE_CLK8:
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clock_bits = 6;
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break;
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case QE_CLK13:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 3:
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switch (clock) {
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case QE_CLK10:
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clock_bits = 6;
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break;
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case QE_CLK15:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 4:
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switch (clock) {
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case QE_CLK12:
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clock_bits = 6;
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break;
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case QE_CLK17:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 5:
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switch (clock) {
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case QE_CLK14:
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clock_bits = 6;
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break;
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case QE_CLK19:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 6:
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switch (clock) {
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case QE_CLK16:
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clock_bits = 6;
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break;
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case QE_CLK21:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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case 7:
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switch (clock) {
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case QE_CLK18:
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clock_bits = 6;
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break;
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case QE_CLK3:
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clock_bits = 7;
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break;
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default:
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break;
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}
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break;
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}
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return clock_bits;
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}
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/* tdm_num: TDM A-H port num is 0-7 */
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static int ucc_get_tdm_rxtx_clk(enum comm_dir mode, u32 tdm_num,
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enum qe_clock clock)
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{
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int clock_bits;
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clock_bits = ucc_get_tdm_common_clk(tdm_num, clock);
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if (clock_bits > 0)
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return clock_bits;
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if (mode == COMM_DIR_RX)
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clock_bits = ucc_get_tdm_rx_clk(tdm_num, clock);
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if (mode == COMM_DIR_TX)
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clock_bits = ucc_get_tdm_tx_clk(tdm_num, clock);
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return clock_bits;
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}
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static u32 ucc_get_tdm_clk_shift(enum comm_dir mode, u32 tdm_num)
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{
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u32 shift;
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shift = (mode == COMM_DIR_RX) ? RX_CLK_SHIFT_BASE : TX_CLK_SHIFT_BASE;
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if (tdm_num < 4)
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shift -= tdm_num * 4;
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else
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shift -= (tdm_num - 4) * 4;
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return shift;
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}
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int ucc_set_tdm_rxtx_clk(u32 tdm_num, enum qe_clock clock,
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enum comm_dir mode)
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{
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int clock_bits;
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u32 shift;
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struct qe_mux __iomem *qe_mux_reg;
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__be32 __iomem *cmxs1cr;
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qe_mux_reg = &qe_immr->qmx;
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if (tdm_num > 7 || tdm_num < 0)
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return -EINVAL;
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/* The communications direction must be RX or TX */
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if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)
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return -EINVAL;
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clock_bits = ucc_get_tdm_rxtx_clk(mode, tdm_num, clock);
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if (clock_bits < 0)
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return -EINVAL;
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shift = ucc_get_tdm_clk_shift(mode, tdm_num);
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cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :
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&qe_mux_reg->cmxsi1cr_h;
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qe_clrsetbits32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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clock_bits << shift);
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return 0;
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}
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static int ucc_get_tdm_sync_source(u32 tdm_num, enum qe_clock clock,
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enum comm_dir mode)
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{
|
|
int source = -EINVAL;
|
|
|
|
if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) {
|
|
source = 0;
|
|
return source;
|
|
}
|
|
if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) {
|
|
source = 0;
|
|
return source;
|
|
}
|
|
|
|
switch (tdm_num) {
|
|
case 0:
|
|
case 1:
|
|
switch (clock) {
|
|
case QE_BRG9:
|
|
source = 1;
|
|
break;
|
|
case QE_BRG10:
|
|
source = 2;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
switch (clock) {
|
|
case QE_BRG9:
|
|
source = 1;
|
|
break;
|
|
case QE_BRG11:
|
|
source = 2;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 4:
|
|
case 5:
|
|
switch (clock) {
|
|
case QE_BRG13:
|
|
source = 1;
|
|
break;
|
|
case QE_BRG14:
|
|
source = 2;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 6:
|
|
case 7:
|
|
switch (clock) {
|
|
case QE_BRG13:
|
|
source = 1;
|
|
break;
|
|
case QE_BRG15:
|
|
source = 2;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
return source;
|
|
}
|
|
|
|
static u32 ucc_get_tdm_sync_shift(enum comm_dir mode, u32 tdm_num)
|
|
{
|
|
u32 shift;
|
|
|
|
shift = (mode == COMM_DIR_RX) ? RX_SYNC_SHIFT_BASE : RX_SYNC_SHIFT_BASE;
|
|
shift -= tdm_num * 2;
|
|
|
|
return shift;
|
|
}
|
|
|
|
int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock,
|
|
enum comm_dir mode)
|
|
{
|
|
int source;
|
|
u32 shift;
|
|
struct qe_mux *qe_mux_reg;
|
|
|
|
qe_mux_reg = &qe_immr->qmx;
|
|
|
|
if (tdm_num >= UCC_TDM_NUM)
|
|
return -EINVAL;
|
|
|
|
/* The communications direction must be RX or TX */
|
|
if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)
|
|
return -EINVAL;
|
|
|
|
source = ucc_get_tdm_sync_source(tdm_num, clock, mode);
|
|
if (source < 0)
|
|
return -EINVAL;
|
|
|
|
shift = ucc_get_tdm_sync_shift(mode, tdm_num);
|
|
|
|
qe_clrsetbits32(&qe_mux_reg->cmxsi1syr,
|
|
QE_CMXUCR_TX_CLK_SRC_MASK << shift,
|
|
source << shift);
|
|
|
|
return 0;
|
|
}
|