827 строки
25 KiB
C
827 строки
25 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/kernel.h>
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#include <linux/component.h>
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#include <drm/i915_component.h>
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#include "intel_drv.h"
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#include <drm/drmP.h>
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#include <drm/drm_edid.h>
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#include "i915_drv.h"
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/**
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* DOC: High Definition Audio over HDMI and Display Port
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*
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* The graphics and audio drivers together support High Definition Audio over
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* HDMI and Display Port. The audio programming sequences are divided into audio
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* codec and controller enable and disable sequences. The graphics driver
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* handles the audio codec sequences, while the audio driver handles the audio
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* controller sequences.
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*
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* The disable sequences must be performed before disabling the transcoder or
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* port. The enable sequences may only be performed after enabling the
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* transcoder and port, and after completed link training. Therefore the audio
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* enable/disable sequences are part of the modeset sequence.
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*
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* The codec and controller sequences could be done either parallel or serial,
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* but generally the ELDV/PD change in the codec sequence indicates to the audio
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* driver that the controller sequence should start. Indeed, most of the
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* co-operation between the graphics and audio drivers is handled via audio
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* related registers. (The notable exception is the power management, not
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* covered here.)
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*
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* The struct i915_audio_component is used to interact between the graphics
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* and audio drivers. The struct i915_audio_component_ops *ops in it is
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* defined in graphics driver and called in audio driver. The
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* struct i915_audio_component_audio_ops *audio_ops is called from i915 driver.
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*/
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static const struct {
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int clock;
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u32 config;
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} hdmi_audio_clock[] = {
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{ 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
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{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
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{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
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{ 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
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{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
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{ 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
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{ 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
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{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
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{ 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
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{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
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};
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/* HDMI N/CTS table */
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#define TMDS_297M 297000
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#define TMDS_296M 296703
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static const struct {
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int sample_rate;
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int clock;
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int n;
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int cts;
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} aud_ncts[] = {
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{ 44100, TMDS_296M, 4459, 234375 },
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{ 44100, TMDS_297M, 4704, 247500 },
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{ 48000, TMDS_296M, 5824, 281250 },
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{ 48000, TMDS_297M, 5120, 247500 },
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{ 32000, TMDS_296M, 5824, 421875 },
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{ 32000, TMDS_297M, 3072, 222750 },
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{ 88200, TMDS_296M, 8918, 234375 },
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{ 88200, TMDS_297M, 9408, 247500 },
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{ 96000, TMDS_296M, 11648, 281250 },
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{ 96000, TMDS_297M, 10240, 247500 },
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{ 176400, TMDS_296M, 17836, 234375 },
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{ 176400, TMDS_297M, 18816, 247500 },
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{ 192000, TMDS_296M, 23296, 281250 },
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{ 192000, TMDS_297M, 20480, 247500 },
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};
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/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
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static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
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if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
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break;
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}
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if (i == ARRAY_SIZE(hdmi_audio_clock)) {
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DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
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adjusted_mode->crtc_clock);
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i = 1;
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}
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DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
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hdmi_audio_clock[i].clock,
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hdmi_audio_clock[i].config);
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return hdmi_audio_clock[i].config;
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}
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static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
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if ((rate == aud_ncts[i].sample_rate) &&
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(mode->clock == aud_ncts[i].clock)) {
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return aud_ncts[i].n;
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}
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}
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return 0;
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}
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static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
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{
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int n_low, n_up;
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uint32_t tmp = val;
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n_low = n & 0xfff;
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n_up = (n >> 12) & 0xff;
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tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
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tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
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(n_low << AUD_CONFIG_LOWER_N_SHIFT) |
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AUD_CONFIG_N_PROG_ENABLE);
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return tmp;
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}
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/* check whether N/CTS/M need be set manually */
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static bool audio_rate_need_prog(struct intel_crtc *crtc,
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const struct drm_display_mode *mode)
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{
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if (((mode->clock == TMDS_297M) ||
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(mode->clock == TMDS_296M)) &&
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intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
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return true;
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else
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return false;
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}
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static bool intel_eld_uptodate(struct drm_connector *connector,
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i915_reg_t reg_eldv, uint32_t bits_eldv,
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i915_reg_t reg_elda, uint32_t bits_elda,
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i915_reg_t reg_edid)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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uint8_t *eld = connector->eld;
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uint32_t tmp;
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int i;
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tmp = I915_READ(reg_eldv);
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tmp &= bits_eldv;
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if (!tmp)
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return false;
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tmp = I915_READ(reg_elda);
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tmp &= ~bits_elda;
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I915_WRITE(reg_elda, tmp);
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for (i = 0; i < drm_eld_size(eld) / 4; i++)
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if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
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return false;
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return true;
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}
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static void g4x_audio_codec_disable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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uint32_t eldv, tmp;
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DRM_DEBUG_KMS("Disable audio codec\n");
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tmp = I915_READ(G4X_AUD_VID_DID);
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if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
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eldv = G4X_ELDV_DEVCL_DEVBLC;
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else
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eldv = G4X_ELDV_DEVCTG;
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/* Invalidate ELD */
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tmp = I915_READ(G4X_AUD_CNTL_ST);
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tmp &= ~eldv;
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I915_WRITE(G4X_AUD_CNTL_ST, tmp);
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}
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static void g4x_audio_codec_enable(struct drm_connector *connector,
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struct intel_encoder *encoder,
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const struct drm_display_mode *adjusted_mode)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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uint8_t *eld = connector->eld;
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uint32_t eldv;
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uint32_t tmp;
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int len, i;
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DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
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tmp = I915_READ(G4X_AUD_VID_DID);
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if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
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eldv = G4X_ELDV_DEVCL_DEVBLC;
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else
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eldv = G4X_ELDV_DEVCTG;
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if (intel_eld_uptodate(connector,
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G4X_AUD_CNTL_ST, eldv,
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G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
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G4X_HDMIW_HDMIEDID))
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return;
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tmp = I915_READ(G4X_AUD_CNTL_ST);
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tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
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len = (tmp >> 9) & 0x1f; /* ELD buffer size */
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I915_WRITE(G4X_AUD_CNTL_ST, tmp);
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len = min(drm_eld_size(eld) / 4, len);
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DRM_DEBUG_DRIVER("ELD size %d\n", len);
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for (i = 0; i < len; i++)
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I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
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tmp = I915_READ(G4X_AUD_CNTL_ST);
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tmp |= eldv;
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I915_WRITE(G4X_AUD_CNTL_ST, tmp);
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}
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static void hsw_audio_codec_disable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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enum pipe pipe = intel_crtc->pipe;
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uint32_t tmp;
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DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
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mutex_lock(&dev_priv->av_mutex);
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/* Disable timestamps */
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tmp = I915_READ(HSW_AUD_CFG(pipe));
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp |= AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_UPPER_N_MASK;
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tmp &= ~AUD_CONFIG_LOWER_N_MASK;
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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I915_WRITE(HSW_AUD_CFG(pipe), tmp);
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/* Invalidate ELD */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp &= ~AUDIO_ELD_VALID(pipe);
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tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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mutex_unlock(&dev_priv->av_mutex);
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}
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static void hsw_audio_codec_enable(struct drm_connector *connector,
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struct intel_encoder *encoder,
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const struct drm_display_mode *adjusted_mode)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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enum pipe pipe = intel_crtc->pipe;
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struct i915_audio_component *acomp = dev_priv->audio_component;
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const uint8_t *eld = connector->eld;
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struct intel_digital_port *intel_dig_port =
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enc_to_dig_port(&encoder->base);
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enum port port = intel_dig_port->port;
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uint32_t tmp;
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int len, i;
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int n, rate;
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DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
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pipe_name(pipe), drm_eld_size(eld));
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mutex_lock(&dev_priv->av_mutex);
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/* Enable audio presence detect, invalidate ELD */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp |= AUDIO_OUTPUT_ENABLE(pipe);
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tmp &= ~AUDIO_ELD_VALID(pipe);
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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/*
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* FIXME: We're supposed to wait for vblank here, but we have vblanks
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* disabled during the mode set. The proper fix would be to push the
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* rest of the setup into a vblank work item, queued here, but the
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* infrastructure is not there yet.
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*/
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/* Reset ELD write address */
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tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
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tmp &= ~IBX_ELD_ADDRESS_MASK;
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I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
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/* Up to 84 bytes of hw ELD buffer */
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len = min(drm_eld_size(eld), 84);
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for (i = 0; i < len / 4; i++)
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I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
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/* ELD valid */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp |= AUDIO_ELD_VALID(pipe);
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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/* Enable timestamps */
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tmp = I915_READ(HSW_AUD_CFG(pipe));
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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else
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tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
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tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
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if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
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if (!acomp)
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rate = 0;
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else if (port >= PORT_A && port <= PORT_E)
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rate = acomp->aud_sample_rate[port];
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else {
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DRM_ERROR("invalid port: %d\n", port);
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rate = 0;
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}
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n = audio_config_get_n(adjusted_mode, rate);
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if (n != 0)
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tmp = audio_config_setup_n_reg(n, tmp);
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else
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DRM_DEBUG_KMS("no suitable N value is found\n");
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}
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I915_WRITE(HSW_AUD_CFG(pipe), tmp);
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mutex_unlock(&dev_priv->av_mutex);
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}
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static void ilk_audio_codec_disable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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struct intel_digital_port *intel_dig_port =
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enc_to_dig_port(&encoder->base);
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enum port port = intel_dig_port->port;
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enum pipe pipe = intel_crtc->pipe;
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uint32_t tmp, eldv;
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i915_reg_t aud_config, aud_cntrl_st2;
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DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
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port_name(port), pipe_name(pipe));
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if (WARN_ON(port == PORT_A))
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return;
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if (HAS_PCH_IBX(dev_priv)) {
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aud_config = IBX_AUD_CFG(pipe);
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aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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aud_config = VLV_AUD_CFG(pipe);
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aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
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} else {
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aud_config = CPT_AUD_CFG(pipe);
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aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
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}
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/* Disable timestamps */
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tmp = I915_READ(aud_config);
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp |= AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_UPPER_N_MASK;
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tmp &= ~AUD_CONFIG_LOWER_N_MASK;
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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I915_WRITE(aud_config, tmp);
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eldv = IBX_ELD_VALID(port);
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/* Invalidate ELD */
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tmp = I915_READ(aud_cntrl_st2);
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tmp &= ~eldv;
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I915_WRITE(aud_cntrl_st2, tmp);
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}
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static void ilk_audio_codec_enable(struct drm_connector *connector,
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struct intel_encoder *encoder,
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const struct drm_display_mode *adjusted_mode)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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struct intel_digital_port *intel_dig_port =
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enc_to_dig_port(&encoder->base);
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enum port port = intel_dig_port->port;
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enum pipe pipe = intel_crtc->pipe;
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uint8_t *eld = connector->eld;
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uint32_t eldv;
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uint32_t tmp;
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int len, i;
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i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
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DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
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port_name(port), pipe_name(pipe), drm_eld_size(eld));
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if (WARN_ON(port == PORT_A))
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return;
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/*
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* FIXME: We're supposed to wait for vblank here, but we have vblanks
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* disabled during the mode set. The proper fix would be to push the
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* rest of the setup into a vblank work item, queued here, but the
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* infrastructure is not there yet.
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*/
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if (HAS_PCH_IBX(connector->dev)) {
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hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
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aud_config = IBX_AUD_CFG(pipe);
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aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
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aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
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} else if (IS_VALLEYVIEW(connector->dev) ||
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IS_CHERRYVIEW(connector->dev)) {
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hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
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aud_config = VLV_AUD_CFG(pipe);
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aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
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aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
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} else {
|
|
hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
|
|
aud_config = CPT_AUD_CFG(pipe);
|
|
aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
|
|
aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
|
|
}
|
|
|
|
eldv = IBX_ELD_VALID(port);
|
|
|
|
/* Invalidate ELD */
|
|
tmp = I915_READ(aud_cntrl_st2);
|
|
tmp &= ~eldv;
|
|
I915_WRITE(aud_cntrl_st2, tmp);
|
|
|
|
/* Reset ELD write address */
|
|
tmp = I915_READ(aud_cntl_st);
|
|
tmp &= ~IBX_ELD_ADDRESS_MASK;
|
|
I915_WRITE(aud_cntl_st, tmp);
|
|
|
|
/* Up to 84 bytes of hw ELD buffer */
|
|
len = min(drm_eld_size(eld), 84);
|
|
for (i = 0; i < len / 4; i++)
|
|
I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
|
|
|
|
/* ELD valid */
|
|
tmp = I915_READ(aud_cntrl_st2);
|
|
tmp |= eldv;
|
|
I915_WRITE(aud_cntrl_st2, tmp);
|
|
|
|
/* Enable timestamps */
|
|
tmp = I915_READ(aud_config);
|
|
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
|
|
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
|
|
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
|
|
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
|
|
tmp |= AUD_CONFIG_N_VALUE_INDEX;
|
|
else
|
|
tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
|
|
I915_WRITE(aud_config, tmp);
|
|
}
|
|
|
|
/**
|
|
* intel_audio_codec_enable - Enable the audio codec for HD audio
|
|
* @intel_encoder: encoder on which to enable audio
|
|
*
|
|
* The enable sequences may only be performed after enabling the transcoder and
|
|
* port, and after completed link training.
|
|
*/
|
|
void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
|
|
{
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
|
|
const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
|
|
struct drm_connector *connector;
|
|
struct drm_device *dev = encoder->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct i915_audio_component *acomp = dev_priv->audio_component;
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
|
|
enum port port = intel_dig_port->port;
|
|
|
|
connector = drm_select_eld(encoder);
|
|
if (!connector)
|
|
return;
|
|
|
|
DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
|
|
connector->base.id,
|
|
connector->name,
|
|
connector->encoder->base.id,
|
|
connector->encoder->name);
|
|
|
|
/* ELD Conn_Type */
|
|
connector->eld[5] &= ~(3 << 2);
|
|
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
|
|
connector->eld[5] |= (1 << 2);
|
|
|
|
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
|
|
|
|
if (dev_priv->display.audio_codec_enable)
|
|
dev_priv->display.audio_codec_enable(connector, intel_encoder,
|
|
adjusted_mode);
|
|
|
|
mutex_lock(&dev_priv->av_mutex);
|
|
intel_dig_port->audio_connector = connector;
|
|
/* referred in audio callbacks */
|
|
dev_priv->dig_port_map[port] = intel_encoder;
|
|
mutex_unlock(&dev_priv->av_mutex);
|
|
|
|
if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
|
|
acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
|
|
}
|
|
|
|
/**
|
|
* intel_audio_codec_disable - Disable the audio codec for HD audio
|
|
* @intel_encoder: encoder on which to disable audio
|
|
*
|
|
* The disable sequences must be performed before disabling the transcoder or
|
|
* port.
|
|
*/
|
|
void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
|
|
{
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
struct drm_device *dev = encoder->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct i915_audio_component *acomp = dev_priv->audio_component;
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
|
|
enum port port = intel_dig_port->port;
|
|
|
|
if (dev_priv->display.audio_codec_disable)
|
|
dev_priv->display.audio_codec_disable(intel_encoder);
|
|
|
|
mutex_lock(&dev_priv->av_mutex);
|
|
intel_dig_port->audio_connector = NULL;
|
|
dev_priv->dig_port_map[port] = NULL;
|
|
mutex_unlock(&dev_priv->av_mutex);
|
|
|
|
if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
|
|
acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
|
|
}
|
|
|
|
/**
|
|
* intel_init_audio_hooks - Set up chip specific audio hooks
|
|
* @dev_priv: device private
|
|
*/
|
|
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
|
|
{
|
|
if (IS_G4X(dev_priv)) {
|
|
dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
|
|
dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
|
|
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
|
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
|
|
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
|
|
} else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
|
|
dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
|
|
dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
|
|
} else if (HAS_PCH_SPLIT(dev_priv)) {
|
|
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
|
|
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
|
|
}
|
|
}
|
|
|
|
static void i915_audio_component_get_power(struct device *dev)
|
|
{
|
|
intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
|
|
}
|
|
|
|
static void i915_audio_component_put_power(struct device *dev)
|
|
{
|
|
intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
|
|
}
|
|
|
|
static void i915_audio_component_codec_wake_override(struct device *dev,
|
|
bool enable)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev_to_i915(dev);
|
|
u32 tmp;
|
|
|
|
if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
|
|
return;
|
|
|
|
/*
|
|
* Enable/disable generating the codec wake signal, overriding the
|
|
* internal logic to generate the codec wake to controller.
|
|
*/
|
|
tmp = I915_READ(HSW_AUD_CHICKENBIT);
|
|
tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
|
|
I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
|
|
usleep_range(1000, 1500);
|
|
|
|
if (enable) {
|
|
tmp = I915_READ(HSW_AUD_CHICKENBIT);
|
|
tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
|
|
I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
|
|
usleep_range(1000, 1500);
|
|
}
|
|
}
|
|
|
|
/* Get CDCLK in kHz */
|
|
static int i915_audio_component_get_cdclk_freq(struct device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev_to_i915(dev);
|
|
|
|
if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
|
|
return -ENODEV;
|
|
|
|
return dev_priv->cdclk_freq;
|
|
}
|
|
|
|
static int i915_audio_component_sync_audio_rate(struct device *dev,
|
|
int port, int rate)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev_to_i915(dev);
|
|
struct intel_encoder *intel_encoder;
|
|
struct intel_crtc *crtc;
|
|
struct drm_display_mode *mode;
|
|
struct i915_audio_component *acomp = dev_priv->audio_component;
|
|
enum pipe pipe = INVALID_PIPE;
|
|
u32 tmp;
|
|
int n;
|
|
int err = 0;
|
|
|
|
/* HSW, BDW, SKL, KBL need this fix */
|
|
if (!IS_SKYLAKE(dev_priv) &&
|
|
!IS_KABYLAKE(dev_priv) &&
|
|
!IS_BROADWELL(dev_priv) &&
|
|
!IS_HASWELL(dev_priv))
|
|
return 0;
|
|
|
|
mutex_lock(&dev_priv->av_mutex);
|
|
/* 1. get the pipe */
|
|
intel_encoder = dev_priv->dig_port_map[port];
|
|
/* intel_encoder might be NULL for DP MST */
|
|
if (!intel_encoder || !intel_encoder->base.crtc ||
|
|
intel_encoder->type != INTEL_OUTPUT_HDMI) {
|
|
DRM_DEBUG_KMS("no valid port %c\n", port_name(port));
|
|
err = -ENODEV;
|
|
goto unlock;
|
|
}
|
|
crtc = to_intel_crtc(intel_encoder->base.crtc);
|
|
pipe = crtc->pipe;
|
|
if (pipe == INVALID_PIPE) {
|
|
DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
|
|
err = -ENODEV;
|
|
goto unlock;
|
|
}
|
|
|
|
DRM_DEBUG_KMS("pipe %c connects port %c\n",
|
|
pipe_name(pipe), port_name(port));
|
|
mode = &crtc->config->base.adjusted_mode;
|
|
|
|
/* port must be valid now, otherwise the pipe will be invalid */
|
|
acomp->aud_sample_rate[port] = rate;
|
|
|
|
/* 2. check whether to set the N/CTS/M manually or not */
|
|
if (!audio_rate_need_prog(crtc, mode)) {
|
|
tmp = I915_READ(HSW_AUD_CFG(pipe));
|
|
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
|
|
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
|
|
goto unlock;
|
|
}
|
|
|
|
n = audio_config_get_n(mode, rate);
|
|
if (n == 0) {
|
|
DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
|
|
port_name(port));
|
|
tmp = I915_READ(HSW_AUD_CFG(pipe));
|
|
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
|
|
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
|
|
goto unlock;
|
|
}
|
|
|
|
/* 3. set the N/CTS/M */
|
|
tmp = I915_READ(HSW_AUD_CFG(pipe));
|
|
tmp = audio_config_setup_n_reg(n, tmp);
|
|
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
|
|
|
|
unlock:
|
|
mutex_unlock(&dev_priv->av_mutex);
|
|
return err;
|
|
}
|
|
|
|
static int i915_audio_component_get_eld(struct device *dev, int port,
|
|
bool *enabled,
|
|
unsigned char *buf, int max_bytes)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev_to_i915(dev);
|
|
struct intel_encoder *intel_encoder;
|
|
struct intel_digital_port *intel_dig_port;
|
|
const u8 *eld;
|
|
int ret = -EINVAL;
|
|
|
|
mutex_lock(&dev_priv->av_mutex);
|
|
intel_encoder = dev_priv->dig_port_map[port];
|
|
/* intel_encoder might be NULL for DP MST */
|
|
if (intel_encoder) {
|
|
ret = 0;
|
|
intel_dig_port = enc_to_dig_port(&intel_encoder->base);
|
|
*enabled = intel_dig_port->audio_connector != NULL;
|
|
if (*enabled) {
|
|
eld = intel_dig_port->audio_connector->eld;
|
|
ret = drm_eld_size(eld);
|
|
memcpy(buf, eld, min(max_bytes, ret));
|
|
}
|
|
}
|
|
|
|
mutex_unlock(&dev_priv->av_mutex);
|
|
return ret;
|
|
}
|
|
|
|
static const struct i915_audio_component_ops i915_audio_component_ops = {
|
|
.owner = THIS_MODULE,
|
|
.get_power = i915_audio_component_get_power,
|
|
.put_power = i915_audio_component_put_power,
|
|
.codec_wake_override = i915_audio_component_codec_wake_override,
|
|
.get_cdclk_freq = i915_audio_component_get_cdclk_freq,
|
|
.sync_audio_rate = i915_audio_component_sync_audio_rate,
|
|
.get_eld = i915_audio_component_get_eld,
|
|
};
|
|
|
|
static int i915_audio_component_bind(struct device *i915_dev,
|
|
struct device *hda_dev, void *data)
|
|
{
|
|
struct i915_audio_component *acomp = data;
|
|
struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
|
|
int i;
|
|
|
|
if (WARN_ON(acomp->ops || acomp->dev))
|
|
return -EEXIST;
|
|
|
|
drm_modeset_lock_all(dev_priv->dev);
|
|
acomp->ops = &i915_audio_component_ops;
|
|
acomp->dev = i915_dev;
|
|
BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
|
|
for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
|
|
acomp->aud_sample_rate[i] = 0;
|
|
dev_priv->audio_component = acomp;
|
|
drm_modeset_unlock_all(dev_priv->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void i915_audio_component_unbind(struct device *i915_dev,
|
|
struct device *hda_dev, void *data)
|
|
{
|
|
struct i915_audio_component *acomp = data;
|
|
struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
|
|
|
|
drm_modeset_lock_all(dev_priv->dev);
|
|
acomp->ops = NULL;
|
|
acomp->dev = NULL;
|
|
dev_priv->audio_component = NULL;
|
|
drm_modeset_unlock_all(dev_priv->dev);
|
|
}
|
|
|
|
static const struct component_ops i915_audio_component_bind_ops = {
|
|
.bind = i915_audio_component_bind,
|
|
.unbind = i915_audio_component_unbind,
|
|
};
|
|
|
|
/**
|
|
* i915_audio_component_init - initialize and register the audio component
|
|
* @dev_priv: i915 device instance
|
|
*
|
|
* This will register with the component framework a child component which
|
|
* will bind dynamically to the snd_hda_intel driver's corresponding master
|
|
* component when the latter is registered. During binding the child
|
|
* initializes an instance of struct i915_audio_component which it receives
|
|
* from the master. The master can then start to use the interface defined by
|
|
* this struct. Each side can break the binding at any point by deregistering
|
|
* its own component after which each side's component unbind callback is
|
|
* called.
|
|
*
|
|
* We ignore any error during registration and continue with reduced
|
|
* functionality (i.e. without HDMI audio).
|
|
*/
|
|
void i915_audio_component_init(struct drm_i915_private *dev_priv)
|
|
{
|
|
int ret;
|
|
|
|
ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
|
|
if (ret < 0) {
|
|
DRM_ERROR("failed to add audio component (%d)\n", ret);
|
|
/* continue with reduced functionality */
|
|
return;
|
|
}
|
|
|
|
dev_priv->audio_component_registered = true;
|
|
}
|
|
|
|
/**
|
|
* i915_audio_component_cleanup - deregister the audio component
|
|
* @dev_priv: i915 device instance
|
|
*
|
|
* Deregisters the audio component, breaking any existing binding to the
|
|
* corresponding snd_hda_intel driver's master component.
|
|
*/
|
|
void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
|
|
{
|
|
if (!dev_priv->audio_component_registered)
|
|
return;
|
|
|
|
component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
|
|
dev_priv->audio_component_registered = false;
|
|
}
|