385 строки
9.2 KiB
C
385 строки
9.2 KiB
C
/*
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* linux/arch/arm/mach-omap2/cpuidle34xx.c
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*
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* OMAP3 CPU IDLE Routines
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*
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* Copyright (C) 2008 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Karthik Dasu <karthik-dp@ti.com>
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*
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* Copyright (C) 2006 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap2
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/cpuidle.h>
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#include <linux/export.h>
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#include <linux/cpu_pm.h>
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#include <plat/prcm.h>
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#include <plat/irqs.h>
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#include "powerdomain.h"
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#include "clockdomain.h"
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#include "pm.h"
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#include "control.h"
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#include "common.h"
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#ifdef CONFIG_CPU_IDLE
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/* Mach specific information to be recorded in the C-state driver_data */
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struct omap3_idle_statedata {
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u32 mpu_state;
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u32 core_state;
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};
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struct omap3_idle_statedata omap3_idle_data[] = {
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{
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.mpu_state = PWRDM_POWER_ON,
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.core_state = PWRDM_POWER_ON,
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},
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{
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.mpu_state = PWRDM_POWER_ON,
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.core_state = PWRDM_POWER_ON,
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},
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{
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.mpu_state = PWRDM_POWER_RET,
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.core_state = PWRDM_POWER_ON,
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},
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{
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.mpu_state = PWRDM_POWER_OFF,
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.core_state = PWRDM_POWER_ON,
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},
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{
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.mpu_state = PWRDM_POWER_RET,
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.core_state = PWRDM_POWER_RET,
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},
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{
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.mpu_state = PWRDM_POWER_OFF,
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.core_state = PWRDM_POWER_RET,
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},
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{
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.mpu_state = PWRDM_POWER_OFF,
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.core_state = PWRDM_POWER_OFF,
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},
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};
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struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
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static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
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struct clockdomain *clkdm)
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{
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clkdm_allow_idle(clkdm);
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return 0;
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}
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static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
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struct clockdomain *clkdm)
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{
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clkdm_deny_idle(clkdm);
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return 0;
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}
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static int __omap3_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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struct omap3_idle_statedata *cx = &omap3_idle_data[index];
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u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
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local_fiq_disable();
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pwrdm_set_next_pwrst(mpu_pd, mpu_state);
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pwrdm_set_next_pwrst(core_pd, core_state);
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if (omap_irq_pending() || need_resched())
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goto return_sleep_time;
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/* Deny idle for C1 */
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if (index == 0) {
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pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
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pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
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}
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/*
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* Call idle CPU PM enter notifier chain so that
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* VFP context is saved.
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*/
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if (mpu_state == PWRDM_POWER_OFF)
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cpu_pm_enter();
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/* Execute ARM wfi */
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omap_sram_idle();
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/*
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* Call idle CPU PM enter notifier chain to restore
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* VFP context.
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*/
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if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
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cpu_pm_exit();
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/* Re-allow idle for C1 */
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if (index == 0) {
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pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
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pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
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}
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return_sleep_time:
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local_fiq_enable();
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return index;
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}
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/**
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* omap3_enter_idle - Programs OMAP3 to enter the specified state
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* @dev: cpuidle device
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* @drv: cpuidle driver
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* @index: the index of state to be entered
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*
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* Called from the CPUidle framework to program the device to the
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* specified target state selected by the governor.
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*/
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static inline int omap3_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
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}
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/**
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* next_valid_state - Find next valid C-state
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* @dev: cpuidle device
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* @drv: cpuidle driver
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* @index: Index of currently selected c-state
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*
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* If the state corresponding to index is valid, index is returned back
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* to the caller. Else, this function searches for a lower c-state which is
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* still valid (as defined in omap3_power_states[]) and returns its index.
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*
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* A state is valid if the 'valid' field is enabled and
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* if it satisfies the enable_off_mode condition.
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*/
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static int next_valid_state(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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struct omap3_idle_statedata *cx = &omap3_idle_data[index];
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u32 mpu_deepest_state = PWRDM_POWER_RET;
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u32 core_deepest_state = PWRDM_POWER_RET;
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int idx;
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int next_index = -1;
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if (enable_off_mode) {
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mpu_deepest_state = PWRDM_POWER_OFF;
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/*
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* Erratum i583: valable for ES rev < Es1.2 on 3630.
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* CORE OFF mode is not supported in a stable form, restrict
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* instead the CORE state to RET.
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*/
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if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
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core_deepest_state = PWRDM_POWER_OFF;
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}
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/* Check if current state is valid */
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if ((cx->mpu_state >= mpu_deepest_state) &&
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(cx->core_state >= core_deepest_state))
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return index;
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/*
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* Drop to next valid state.
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* Start search from the next (lower) state.
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*/
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for (idx = index - 1; idx >= 0; idx--) {
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cx = &omap3_idle_data[idx];
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if ((cx->mpu_state >= mpu_deepest_state) &&
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(cx->core_state >= core_deepest_state)) {
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next_index = idx;
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break;
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}
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}
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/*
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* C1 is always valid.
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* So, no need to check for 'next_index == -1' outside
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* this loop.
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*/
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return next_index;
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}
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/**
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* omap3_enter_idle_bm - Checks for any bus activity
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* @dev: cpuidle device
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* @drv: cpuidle driver
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* @index: array index of target state to be programmed
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*
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* This function checks for any pending activity and then programs
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* the device to the specified or a safer state.
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*/
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static int omap3_enter_idle_bm(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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int new_state_idx;
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u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
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struct omap3_idle_statedata *cx;
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int ret;
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/*
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* Prevent idle completely if CAM is active.
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* CAM does not have wakeup capability in OMAP3.
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*/
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cam_state = pwrdm_read_pwrst(cam_pd);
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if (cam_state == PWRDM_POWER_ON) {
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new_state_idx = drv->safe_state_index;
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goto select_state;
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}
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/*
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* FIXME: we currently manage device-specific idle states
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* for PER and CORE in combination with CPU-specific
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* idle states. This is wrong, and device-specific
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* idle management needs to be separated out into
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* its own code.
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*/
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/*
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* Prevent PER off if CORE is not in retention or off as this
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* would disable PER wakeups completely.
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*/
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cx = &omap3_idle_data[index];
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core_next_state = cx->core_state;
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per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
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if ((per_next_state == PWRDM_POWER_OFF) &&
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(core_next_state > PWRDM_POWER_RET))
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per_next_state = PWRDM_POWER_RET;
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/* Are we changing PER target state? */
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if (per_next_state != per_saved_state)
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pwrdm_set_next_pwrst(per_pd, per_next_state);
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new_state_idx = next_valid_state(dev, drv, index);
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select_state:
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ret = omap3_enter_idle(dev, drv, new_state_idx);
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/* Restore original PER state if it was modified */
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if (per_next_state != per_saved_state)
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pwrdm_set_next_pwrst(per_pd, per_saved_state);
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return ret;
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}
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DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
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struct cpuidle_driver omap3_idle_driver = {
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.name = "omap3_idle",
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.owner = THIS_MODULE,
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.states = {
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{
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.enter = omap3_enter_idle,
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.exit_latency = 2 + 2,
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.target_residency = 5,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C1",
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.desc = "MPU ON + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 10 + 10,
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.target_residency = 30,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C2",
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.desc = "MPU ON + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 50 + 50,
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.target_residency = 300,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C3",
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.desc = "MPU RET + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 1500 + 1800,
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.target_residency = 4000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C4",
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.desc = "MPU OFF + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 2500 + 7500,
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.target_residency = 12000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C5",
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.desc = "MPU RET + CORE RET",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 3000 + 8500,
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.target_residency = 15000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C6",
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.desc = "MPU OFF + CORE RET",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 10000 + 30000,
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.target_residency = 30000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C7",
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.desc = "MPU OFF + CORE OFF",
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},
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},
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.state_count = ARRAY_SIZE(omap3_idle_data),
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.safe_state_index = 0,
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};
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/**
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* omap3_idle_init - Init routine for OMAP3 idle
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*
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* Registers the OMAP3 specific cpuidle driver to the cpuidle
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* framework with the valid set of states.
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*/
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int __init omap3_idle_init(void)
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{
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struct cpuidle_device *dev;
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mpu_pd = pwrdm_lookup("mpu_pwrdm");
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core_pd = pwrdm_lookup("core_pwrdm");
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per_pd = pwrdm_lookup("per_pwrdm");
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cam_pd = pwrdm_lookup("cam_pwrdm");
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cpuidle_register_driver(&omap3_idle_driver);
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dev = &per_cpu(omap3_idle_dev, smp_processor_id());
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dev->cpu = 0;
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if (cpuidle_register_device(dev)) {
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printk(KERN_ERR "%s: CPUidle register device failed\n",
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__func__);
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return -EIO;
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}
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return 0;
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}
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#else
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int __init omap3_idle_init(void)
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{
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return 0;
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}
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#endif /* CONFIG_CPU_IDLE */
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